Virtual Workshop on “Next Generation Computing in the Era of Chiplets”

Date: April 2, 2025

Start Time: 9:30am (CDT)

Timezone – Central

Length/ Duration: 90 minutes

Kick Off – Moitreyee Mukherjee-Roy (IBM) TC19 Chair

Speaker 1 – Joshua Rubin (IBM)

Title – Memory challenges and solutions for chiplets

ABSTRACT – The AI hardware industry landscape is full of diverse approaches to hardware design, ranging from large SoCs to chipletized systems based on both 3D and 2.xD packaging.  Even within the chipletized systems the chiplet architecture can vary greatly. Most current solutions are based on silicon designed by a single hardware vendor. In this workshop we will review the AI hardware industry landscape and compare the various approaches. Furthermore, we will explore a vision for disaggregation of IBM’s recently announced Spyre accelerator SoC, designed by IBM Research. We will look at how an AI chiplet in combination with other chiplets in an open chiplet ecosystem would enable creation of performant chiplet architectures for domain-specific applications.

Short BIO :

Joshua Rubin is a Senior Engineer at IBM, where he has been technical lead on projects dealing with wafer scale 3D integration, system performance analysis for novel technical elements, heterogeneous integration, and AI hardware design. An IBM Master Inventor, he holds over 90 patents in transistor design and integration, power distribution, 3D integration, packaging, and memory devices. He earned a PhD in electrical engineering at Cornell University. He has also published several technical articles and presented at several conferences including the Electronic Components and Technology Conference (ECTC), IEEE Journal of Solid-State Circuits (ISSCC), IEEE Electron Device Letters (EDL), and IEEE International Conference on MEMS. Most recently he was a technical lead for the packaging and card design of IBM’s latest Artificial Intelligence Unit (AIU) product.

Speaker 2 – Srikanth Rangarajan

Title: Advanced Thermal Management of Next-Generation of High-Performance Computing

Abstract: As high-performance computing (HPC) systems continue to evolve, the challenge of managing heat generated by increasingly powerful and compact electronic components has become paramount. This talk explores cutting-edge thermal management solutions that are paving the way for the next generation of HPC systems. We will discuss innovative approaches such as single- and two-phase liquid cooling. The presentation will also cover advancements in phase change materials for managing transient heat loads.  Additionally, the talk will examine the integration of artificial intelligence and machine learning into thermal management systems, enabling real-time temperature monitoring and predictive analysis for optimal cooling strategies. The talk will highlight how these technologies are not only addressing current thermal challenges but also enabling the development of more powerful, efficient, and reliable HPC systems for the future.

Short BIO:

Srikanth Rangarajan currently works as an Assistant Professor in the School of System Science and Industrial Engineering at Binghamton University. He received his M.S & Ph.D. in Mechanical Engineering from the Indian Institute of Technology Madras 2017. His research interests include Energy Storage management systems, electronic packaging, Digital twinning for electronics and batteries, Thermal energy storage, Thermal Management of electronics, and Data center cooling. Srikanth has published 35 international journal articles so far. Srikanth is also the author of the book “Phase Change Material Heat Sinks: A multi-objective Perspective.”

Prior to joining the School of System Science and Industrial Engineering, Srikanth worked as an Associate Research Professor in the Department of Mechanical Engineering at SUNY Binghamton

Research Interests

• Thermal management, optimization, Digital Twinning and sustainability of electronic systems
• Advanced packaging and heterogeneous integration of electronic systems
• Data Center cooling
• Digital twinning and optimization of battery systems
• Thermal Energy Storage: Design and optimization

Speaker 3 – Si-Ping Gao:

Title – Power Delivery of Heterogeneous Integration: Challenges and Opportunities

As semiconductor design continues to evolve, chiplet technology has emerged as a promising solution to the limitations of traditional monolithic integrated circuits [1]. The shift towards chiplet-based heterogeneous integration (HI) offers flexibility, scalability, and improved manufacturing yields. However, this new approach presents significant challenges in power delivery. Efficient power delivery in HI systems is crucial to maintaining performance and reliability across multiple, independently manufactured and assembled die [2]. In this paper, we explore the key issues surrounding power delivery in HI architectures, including power integrity, voltage regulation, interconnect design, and thermal management [3]. We also propose innovative power delivery network (PDN) strategies tailored to the specific needs of chiplet designs. Our findings demonstrate how advanced PDN designs can mitigate power-related issues while supporting the energy efficiency, performance, and scalability demands of future semiconductor systems. This talk provides valuable insights for industry professionals and academics aiming to address the power delivery challenges inherent in the next generation of chiplet-based HI technologies.

References

[1]        K. Radhakrishnan, M. Swaminathan, and B. K. Bhattacharyya, “Power Delivery for High-Performance Microprocessors – Challenges, Solutions, and Future Trends,” IEEE Trans. Compon. Packag. Manuf. Technol, vol. 11, no. 4, pp. 655–671, Apr. 2021.

[2]        J. Kim et al., “Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse,” IEEE Trans. Very Large Scale Integr. Syst., vol. 28, no. 11, pp. 2424–2437, Nov. 2020.

[3]        J. Kim et al., “Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs,” IEEE Trans. Compon. Packag. Manuf. Technol, vol. 11, no. 12, pp. 2148–2157, Dec. 2021.

Short Bio:

Si-Ping Gao (Senior Member, IEEE) received the B.Eng., M.Eng. and D.Eng. degrees in electronic engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2007, 2009, and 2013, respectively.

From 2013 to 2017, he was a Scientist with the Department of Electronics and Photonics, Institute of High Performance Computing (IHPC), A*STAR, Singapore. From 2017 to 2022, he was a Research Fellow in the Department of Electrical and Computer Engineering, National University of Singapore (NUS). From 2022 to 2024, he was a Senior Engineer of AMD. He is currently a Full Professor of NUAA. He has authored more than 100 refereed papers and one book chapter. He holds several patents. His research interests include EMC/EMI, signal and power integrity for 2.5D/3D ICs, and RFICs.

Dr. Gao received the Young Professional Award from the IEEE EMC Society in 2021 and many other technical awards including the APEMC 2016 Best Symposium Paper Award, the SPI 2017 Young Investigator Training Program Award, the URSI GASS 2017 Young Scientist Award, the Outstanding Young Scientist Award at the 2018 Joint IEEE EMC & APEMC Symposium, and the IEEE MTT-S IMWS-AMP 2020 Best Paper Award. He served as the TPC Chair and Co-chair of IEEE MTT-S IMWS-AMP 2025 and 2021, respectively, the Technical Paper Chair of APEMC 2022. He was a Distinguished Reviewer of IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY in 2023. He has been serving the IEEE EMC Singapore Chapter since 2016.