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the IEEE Nanotechnology Council!
January 12th, 2022
January 12th, 2022
IEEE NTC Facebook website is linked below. It can also be linked to by the Facebook option at the upper right corner of the front page of the NTC website.
NTC officers, members, conference/workshop organizers are invited to join it and post relevant information.
Open website in which only authorized members are allowed to post articles:
http://www.facebook.com/groups/ieeenanotechnology/ (https://www.facebook.com/groups/550239578466583/)
January 12th, 2022
The NTC has several Linked-in sites:
Main NTC ‘company’ page: https://www.linkedin.com/company/ieee-ntc
NTC Women in Nanotechnology (WIN) ‘company’ page: https://linkedin.com/company/ieee-nanotechnology-council-women-in-nanotechnology
NTC Young Professionals (YP):
- Region 7: https://www.linkedin.com/company/ieee-ntc-yp-canada/
- Region 8: https://www.linkedin.com/company/ieee-ntc-young-professionals-r8
- Region 9: https://www.linkedin.com/company/ieee-ntc-yp-r9
- Region 10: https://www.linkedin.com/company/ieee-ntc-yp-r10-ap/
IEEE-NANO Conference: https://www.linkedin.com/company/ieee-nano-conferences
March 19th, 2025
Virtual Workshop on “Next Generation Computing in the Era of Chiplets”
Kick Off – Moitreyee Mukherjee-Roy (IBM) TC19 Chair
Speaker 1 – Joshua Rubin (IBM)
Title – Memory challenges and solutions for chiplets
ABSTRACT – The AI hardware industry landscape is full of diverse approaches to hardware design, ranging from large SoCs to chipletized systems based on both 3D and 2.xD packaging. Even within the chipletized systems the chiplet architecture can vary greatly. Most current solutions are based on silicon designed by a single hardware vendor. In this workshop we will review the AI hardware industry landscape and compare the various approaches. Furthermore, we will explore a vision for disaggregation of IBM’s recently announced Spyre accelerator SoC, designed by IBM Research. We will look at how an AI chiplet in combination with other chiplets in an open chiplet ecosystem would enable creation of performant chiplet architectures for domain-specific applications.
Short BIO :
Joshua Rubin is a Senior Engineer at IBM, where he has been technical lead on projects dealing with wafer scale 3D integration, system performance analysis for novel technical elements, heterogeneous integration, and AI hardware design. An IBM Master Inventor, he holds over 90 patents in transistor design and integration, power distribution, 3D integration, packaging, and memory devices. He earned a PhD in electrical engineering at Cornell University. He has also published several technical articles and presented at several conferences including the Electronic Components and Technology Conference (ECTC), IEEE Journal of Solid-State Circuits (ISSCC), IEEE Electron Device Letters (EDL), and IEEE International Conference on MEMS. Most recently he was a technical lead for the packaging and card design of IBM’s latest Artificial Intelligence Unit (AIU) product.
Speaker 2 – Srikanth Rangarajan
Title: Advanced Thermal Management of Next-Generation of High-Performance Computing
Abstract: As high-performance computing (HPC) systems continue to evolve, the challenge of managing heat generated by increasingly powerful and compact electronic components has become paramount. This talk explores cutting-edge thermal management solutions that are paving the way for the next generation of HPC systems. We will discuss innovative approaches such as single- and two-phase liquid cooling. The presentation will also cover advancements in phase change materials for managing transient heat loads. Additionally, the talk will examine the integration of artificial intelligence and machine learning into thermal management systems, enabling real-time temperature monitoring and predictive analysis for optimal cooling strategies. The talk will highlight how these technologies are not only addressing current thermal challenges but also enabling the development of more powerful, efficient, and reliable HPC systems for the future.
Short BIO:
Srikanth Rangarajan currently works as an Assistant Professor in the School of System Science and Industrial Engineering at Binghamton University. He received his M.S & Ph.D. in Mechanical Engineering from the Indian Institute of Technology Madras 2017. His research interests include Energy Storage management systems, electronic packaging, Digital twinning for electronics and batteries, Thermal energy storage, Thermal Management of electronics, and Data center cooling. Srikanth has published 35 international journal articles so far. Srikanth is also the author of the book “Phase Change Material Heat Sinks: A multi-objective Perspective.”
Prior to joining the School of System Science and Industrial Engineering, Srikanth worked as an Associate Research Professor in the Department of Mechanical Engineering at SUNY Binghamton
Research Interests
- Thermal management, optimization, Digital Twinning and sustainability of electronic systems
- Advanced packaging and heterogeneous integration of electronic systems
- Data Center cooling
- Digital twinning and optimization of battery systems
- Thermal Energy Storage: Design and optimization
Speaker 3 – Si-Ping Gao:
Title – Power Delivery of Heterogeneous Integration: Challenges and Opportunities
As semiconductor design continues to evolve, chiplet technology has emerged as a promising solution to the limitations of traditional monolithic integrated circuits [1]. The shift towards chiplet-based heterogeneous integration (HI) offers flexibility, scalability, and improved manufacturing yields. However, this new approach presents significant challenges in power delivery. Efficient power delivery in HI systems is crucial to maintaining performance and reliability across multiple, independently manufactured and assembled die [2]. In this paper, we explore the key issues surrounding power delivery in HI architectures, including power integrity, voltage regulation, interconnect design, and thermal management [3]. We also propose innovative power delivery network (PDN) strategies tailored to the specific needs of chiplet designs. Our findings demonstrate how advanced PDN designs can mitigate power-related issues while supporting the energy efficiency, performance, and scalability demands of future semiconductor systems. This talk provides valuable insights for industry professionals and academics aiming to address the power delivery challenges inherent in the next generation of chiplet-based HI technologies.
References
[1] K. Radhakrishnan, M. Swaminathan, and B. K. Bhattacharyya, “Power Delivery for High-Performance Microprocessors – Challenges, Solutions, and Future Trends,” IEEE Trans. Compon. Packag. Manuf. Technol, vol. 11, no. 4, pp. 655–671, Apr. 2021.
[2] J. Kim et al., “Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse,” IEEE Trans. Very Large Scale Integr. Syst., vol. 28, no. 11, pp. 2424–2437, Nov. 2020.
[3] J. Kim et al., “Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs,” IEEE Trans. Compon. Packag. Manuf. Technol, vol. 11, no. 12, pp. 2148–2157, Dec. 2021.
Short Bio:
Si-Ping Gao (Senior Member, IEEE) received the B.Eng., M.Eng. and D.Eng. degrees in electronic engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2007, 2009, and 2013, respectively.
From 2013 to 2017, he was a Scientist with the Department of Electronics and Photonics, Institute of High Performance Computing (IHPC), A*STAR, Singapore. From 2017 to 2022, he was a Research Fellow in the Department of Electrical and Computer Engineering, National University of Singapore (NUS). From 2022 to 2024, he was a Senior Engineer of AMD. He is currently a Full Professor of NUAA. He has authored more than 100 refereed papers and one book chapter. He holds several patents. His research interests include EMC/EMI, signal and power integrity for 2.5D/3D ICs, and RFICs.
Dr. Gao received the Young Professional Award from the IEEE EMC Society in 2021 and many other technical awards including the APEMC 2016 Best Symposium Paper Award, the SPI 2017 Young Investigator Training Program Award, the URSI GASS 2017 Young Scientist Award, the Outstanding Young Scientist Award at the 2018 Joint IEEE EMC & APEMC Symposium, and the IEEE MTT-S IMWS-AMP 2020 Best Paper Award. He served as the TPC Chair and Co-chair of IEEE MTT-S IMWS-AMP 2025 and 2021, respectively, the Technical Paper Chair of APEMC 2022. He was a Distinguished Reviewer of IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY in 2023. He has been serving the IEEE EMC Singapore Chapter since 2016.
March 12th, 2025
Website URL: http://ieee-nanomed.org/2025/
Date: 1 – 4 December
Venue: Hong Kong, China
IEEE-NANOMED is one of the premier annual events organized by the IEEE Nanotechnology Council (NTC), and brings together physicians, scientists, and engineers from all over the world and every sector of academy and industry for the advancement of basic and clinical research in medical and biological sciences through nano/molecular medicine and engineering. Attendees of IEEE-NANOMED can share their latest research in engineering and nano/molecular medicine with other practitioners in their field and related fields, ranging from basic scientific and engineering research to translational and clinical research.
Important Dates:
Two-Page Abstract Deadline: 11 July 2025
Notification of Acceptance: 12 September 2025
Full Paper Deadline: 12 July 2025 (for best paper competition)
3 October 2025 (for inclusion in IEEE Xplore)
Early Bird Registration: 30 September 2025
March 5th, 2025
Date: May 20th, 2025
Time: 11:00AM Eastern Daylight Time (Montreal)
Title: Technology Computer-Aided Design and Ab Initio Simulations of Quantum-Technology Hardware
Speaker: Félix Beaudoin, Ph.D. Director of Quantum Technology, Nanoacademic Technologies Inc.
Organizer: TC10 mentee member, Luiz Felipe Aguinsky
Register below to receive meeting link.
Abstract:
Quantum technologies are poised to revolutionize sensing, cryptography, and computing by leveraging the deepest quantum-mechanical effects such as quantum superposition and entanglement. However, quantum advantage relies upon quantum hardware such as superconducting qubits or spin qubits in semiconductors, which suffers from several defects and imperfections that may lead to decoherence. In addition, quantum-hardware design, prototyping, and characterization workflows that do not leverage mature and predictive technology computer-aided design (TCAD) simulation software often rely on excessive trial and error with real-world devices. This approach incurs high manufacturing and personnel cost and may even result in quantum devices that fail to
meet performance requirements. In this webinar, we describe how Nanoacademic Technologies’ ab initio (RESCU, NanoDCAL) and quantum TCAD (QTCAD®) software can be used for atomistic and TCAD modeling of quantum
devices, akin to simulation and design workflows employed for standard semiconductor devices and materials. We will show how recent functional and performance advances in the QTCAD® software led to the demonstration
of quantitatively predictive simulations of spin qubits in semiconductor gated quantum dots. In addition, we will describe how combining QTCAD® features with the large-scale density functional theory (DFT) software
RESCU enabled calculating the addition energy of a single-phosphorus-donor spin qubit in silicon completely from first
principles for a system containing more than 10,000 atoms. Finally, future applications of QTCAD®, RESCU, and NanoDCAL for superconducting-qubit device and materials modeling will be explored.
Bio:
Félix Beaudoin is the Director of Quantum Technology and a Research Scientist at Nanoacademic Technologies Inc., a scientific software company based in Montréal, Québec, Canada. He first obtained an M. Sc. in theoretical physics from Université de Sherbrooke in 2011 under the supervision of Prof. Alexandre Blais, followed by a Ph.D. in theoretical
physics from McGill University in 2016 with Prof. William A. Coish. In 2017-2018, Félix Beaudoin worked as a postdoctoral associate and university lecturer at Dartmouth College in the research group of Prof.
Lorenza Viola, in close collaboration with the Quantum Information and Integrated Nanosystems Group led by Prof. William D. Oliver (Massachusetts Institute of Technology). Félix Beaudoin’s research interests are focused on quantum-technology topics such as quantum noise, quantum control, quantum computing, quantum metrology, and modeling of spin qubits and superconducting qubits alike.
Félix Beaudoin joined Nanoacademic in 2019 as a Research Scientist and became the company’s Director of Quantum Technology in 2021. With a team of experts, he manages the development of Nanoacademic’s newest quantum modeling tool: QTCAD®.
Register for meeting link:
March 4th, 2025
The IEEE Nanotechnology Council is pleased to announce the appointments of Distinguished Lecturers for 2025.
| José Miguel García-Martín | 1. Nanostructured columnar thin films by magnetron sputtering: From fundamentals to devices |
| Deep Jariwala | 1. III-Nitride Ferroelectrics for Low-Power and Extreme Environment Electronics
2. Nanoscale Excitonic Semiconductors for Strong Light-Matter Interactions 3. Two-Dimensional Semiconductors for Low-Power Logic and Memory Devices |
| Davide Mencarelli | 1. Advanced modeling and design of RF devices and systems based on low-dimensional materials
2. Development of multi-physic and multi-scale models of electro/opto- mechanical systems forhigh-frequency devices 3. Rigorous numerical simulation of the combine quantum-electromagnetic problem for application to nonlinear device |
| Federico Rosei | 1. Multifunctional materials for emerging solar technologies 2D Conjugated Polymers: Organic Analogues of Graphene |
| Wenzhuo Wu | 1. Tellurene electronics and beyond |
February 28th, 2025
Greetings from IEEE NTC President Jin-Woo Kim
As I enter my second year as the President of the IEEE Nanotechnology Council (NTC), I am honored to reflect on the meaningful progress we have made together and to share my vision for the year ahead. It has been an extraordinary journey working alongside a dedicated team of volunteers, researchers, and professionals who continue to elevate NTC as a global leader in nanotechnology.
The past year has seen steady progress in NTC’s activities. We have strengthened our technical activities, expanded our global outreach, and continued to enhance the impact of our conferences and publications. The growth in participation across various NTC-sponsored initiatives has reaffirmed our commitment to fostering a thriving and inclusive nanotechnology community.
Key milestones from the past year include:
- Continued success of NTC’s technical conferences including our flagship events – IEEE-NANO and IEEE-NMDC.
- Strengthened collaborations with IEEE Societies, Councils, and external organizations to drive interdisciplinary advancements.
- Increased visibility of NTC’s publications, ensuring high-impact research continues to reach a broader audience.
- Ongoing efforts to support young professionals and students through various initiatives, encouraging the next generation of nanotechnology leaders.
These accomplishments have been possible due to the unwavering dedication of our volunteers and contributors, and I extend my deepest gratitude to each of you!
However, this past year has not been without challenges. A significant change in IEEE’s budgetary procedures has introduced new complexities in financial planning and resource allocation. This shift has required us to adapt swiftly to ensure that our programs and initiatives continue without disruption. While we have successfully navigated these changes so far, we must remain diligent in managing our financial health while sustaining our high level of activity.
Building on our progress, we will focus on the following priorities in the coming year:
- Expanding technical and professional opportunities. We aim to continue enhancing the scope of our conferences, technical programs, and educational programs to provide even greater opportunities for networking, collaboration, and knowledge exchange.
- Strengthening strategic partnerships. We will continue to foster meaningful connections with IEEE entities, industry leaders, and global research institutions. These partnerships will drive innovation and create new opportunities for our participants.
- Enhancing diversity and global inclusion. Encouraging broader participation and representation across different regions remains a key goal. We will focus on increasing outreach efforts to underrepresented areas and ensuring that NTC is a truly global platform for nanotechnology professionals.
- Elevating NTC’s publications and technical Excellence. We will continue to uphold the highest standards of technical excellence across our journals and publications while promoting emerging areas of nanotechnology research.
- Empowering the next generation of leaders. Through mentorship programs and outreach efforts, we aim to empower the next generation of nanotechnology professionals, cultivating the future of nanotechnology leadership.
- Navigating financial challenges and ensuring sustainability. With the changes in IEEE’s budgetary procedures, we must find innovative ways to sustain our initiatives while adapting to the new financial landscape. Careful financial planning and efficient resource utilization will be essential for maintaining the quality and impact of our activities.
NTC thrives because of its passionate volunteers and contributors! I encourage each of you to take an active role in shaping the future of our Council. Whether through technical committees, publications, conferences, or outreach programs, your involvement makes a difference – Your involvement is invaluable to our continued growth!
We recognize that the upcoming year presents both opportunities and challenges, but I am confident that, through collaboration and dedication, we will continue to make significant strides in advancing nanotechnology and strengthening our community.
I invite you to stay engaged, share your ideas, and help us propel NTC toward new heights of success. Please feel free to reach out to me at jwkim@uark.edu with your thoughts and suggestions.
Together, let’s continue to make a lasting impact in the field of nanotechnology!
With appreciation and enthusiasm,
Jin-Woo Kim
President, IEEE Nanotechnology Council
February 13th, 2025
Special Topic on Challenges and Opportunities for Information Processing and Storage with Ferroelectric Devices and Circuits
Guest Editor
Sourav Dutta, The University of Texas at Dallas, sourav.dutta@utdallas.edu
Editor-in-Chief
Azad Naeemi, Georgia Institute of Technology, azad@gatech.edu
Aims and Scope
The continued scaling of CMOS has been one of the key drivers towards the progress of modern computing. Miniaturization of advanced logic and memory has allowed us to achieve higher performance, reduced power consumption, and increased storage capacity. As the industry approaches the physical limits of conventional silicon scaling, new materials and devices need to be explored to continue this trend. Furthermore, new forms of computing need to be explored for making breakthrough advancements in hardware accelerator designs that can support the ever-growing size and complexity of the AI models.
Ferroelectric materials, with their unique property of spontaneous polarization that can be reversed by an external electric field, are promising candidates that can augment or replace conventional silicon-based semiconductor devices and act as scaling boosters for memory technology and enable new forms of information processing. For example, ferroelectric materials naturally exhibit non-volatile memory characteristics making them ideal candidates for memory application. By integration ferroelectric materials in the gate stack of a conventional silicon transistor, as an integrated capacitor with an access transistor and as a replacement for conventional charge-trap layers, new memory technologies in the form of ferroelectric field-effect transistor (FeFET), ferroelectric random-access memory (FeRAM) and ferroelectric NAND flash (Fe-NAND) can be realized. These can in turn enable orders of magnitude improvement in the storage capacity, energy-efficiency and latency for cache, DRAM and flash memories. Beyond conventional memories, ferroelectric devices also exhibit unique properties including multilevel polarization states and temporal dynamics, making them suitable for mimicking biological neural networks. As such, building digital, analog or mixed-signal circuits with ferroelectric devices can offer potential breakthroughs in energy-efficient, brain-inspired computing, overcoming the bottleneck of traditional von Neumann computing.
Such promising opportunities also come with practical challenges pertaining to choice of materials, scalability, performance, reliability and integration with CMOS. For example, aggressive scaling of ferroelectric materials for compatibility with advanced CMOS nodes can degrade their inherent ferroelectric behavior. Ferroelectric materials and devices suffer from fatigue, imprint, and retention issues, which can affect their long-term performance and reliability. Achieving high-speed switching comparable to SRAM remains a significant challenge. Finally, conformal deposition of ferroelectric materials with uniform properties across high aspect ratio 3-D structures is challenging, particularly for highly integrated devices.
This special issue of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) aims to call for the recent research advances that address both the challenges and opportunities for information processing and storage with ferroelectric devices and circuits. Papers on co-design and optimization across multiple domains including materials, devices, circuits and architecture/systems are encouraged.
Topics of Interests
Prospective authors are invited to submit original works and/or extended works based on conference presentations on various aspects of information processing and storage with ferroelectric devices and circuits. Topics of special interest include but are not limited to:
- Advancements in ferroelectric materials and devices addressing key challenges
- Across-the-stack co-design and optimization approaches from materials and device to application.
- Monolithic and/or heterogeneous 3D integration with CMOS.
- New digital, analog and mixed-signal circuit design including peripherals for energy-efficient information processing and high-density storage.
- Architectural-level design for energy-efficient information processing and high-density storage.
- Application-level advancements for energy-efficient information processing and high-density storage.
Important Dates
Open for Submission: Feb. 15, 2025
Submission Deadline: May 15, 2025
First Notification: June 15, 2025
Revision Submission: July 1, 2025
Final Decision: July 15, 2025
Publication Online: Aug. 1, 2025
Please refer to the JxCDC website for submission guidelines.
January 29th, 2025
SSCS Webinar Series – Professional Development Networking, and Career Growth
JxCDC SSCS Open Journal Webinar: Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures
Date: 6 February 2025
Time: 2:00 pm – 4:00 pm EST
Location: Webinar – Online
Contact: Aeisha VanBuskirk – a.vanbuskirk@ieee.org
Title: Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures
Abstract: Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. To understand the reasons underlying this trend, we develop a behavioral model of resistive IMCs to analyze the signal-to-noise-plus-distortion ratio (SNDR) of MRAM, ReRAM, and FeFET-based IMCs, employing parameter variation and noise models which are validated w.r.t. measured results from a recent MRAM-based IMC prototype in a 22nm process.
Presenters:
Saion K. Roy Saion K. Roy (Member, IEEE) received his Ph.D. from the University of Illinois at Urbana–Champaign, USA, in 2024, and his B.Tech. and M.Tech. degrees from the Indian Institute of Technology Kharagpur, India, in 2018.
Naresh R. Shanbhag Naresh R. Shanbhag (Fellow, IEEE) received the Ph.D. degree in electrical engineering from the University of Minnesota, Minneapolis, MN, USA, in 1993. He is currently the Jack Kilby Professor of Electrical and Computer Engineering with the University of Illinois at Urbana-Champaign, Champaign, IL, USA.
The IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC) is sponsored by:
IEEE Solid-State Circuits Society
IEEE Magnetics Society
IEEE Circuits and Systems Society
IEEE Electron Devices Society
IEEE Council of Electronic Design Automation
IEEE Council on Superconductivity
IEEE Nanotechnology Council
January 27th, 2025
Website URL: https://2025.ieeenano.org/
Date: 13th – 16th July
Venue: Washington DC, USA
Join us in shaping the future of nanotechnology! Explore cutting-edge research, connect with global experts, and discover ground-breaking innovations at IEEE Nano 2025.
Visit our website for all the details about the conference, including key topics, speakers, workshops, and networking opportunities. Don’t miss your chance to be part of this transformative event in the world of nanotechnology!
Important Dates
4-page Papers
15 Jan – 1 March 2025 10 March 2025
Decision by 5 Apr 2025
1-page Abstracts
15 Jan – 1 April 2025
Decision by 15 Apr 2025
January 24th, 2025
Mark your calendars! Join us on Feb 6th at 2 PM ET for an insightful Open Journal Webinar on “Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures” presented by the exceptional Saion K. Roy and Naresh R. Shanbhag.
Register here: https://bit.ly/4gUonKD
January 20th, 2025
Date: Thursday, March 6, 2025
Time: 17:00 Central European Time
Speaker: Dr. Nicolas Onofrio, Software for Chemistry and Materials (SCM)
Organizer: TC10 mentee member, Luiz Felipe Aguinsky
Title: Exploring Advanced Materials Modeling with the Amsterdam Modeling Suite
Register below to receive meeting link.
Abstract:
In this talk Dr. Nicolas Onofrio will present the Amsterdam Modeling Suite (AMS), a powerful software package for atomistic simulations across diverse levels of theory. AMS offers seamless integration with computational engines such as Density Functional Theory, Tight Binding, and Force Fields, making it an invaluable platform for exploring potential energy surfaces (PES) in molecules and periodic systems. Its innovative features include ParAMS, a module to tune atomistic model parameters as well as an active learning workflow for efficient PES exploration. These capabilities enable rapid predictions of material properties and reaction mechanisms, driving advancements in batteries, semiconductors, polymers, and OLEDs. With an intuitive Python interface, AMS empowers researchers to automate workflows, screen materials, and optimize critical properties, providing a comprehensive toolkit for accelerating innovation in chemistry and materials science.
Bio:
Dr. Nicolas Onofrio is a Technical Sales Representative at Software for Chemistry & Materials (SCM), where he leverages his expertise in computational materials science, theoretical chemistry, and machine learning to support researchers and industries in utilizing the Amsterdam Modeling Suite (AMS). Dr. Onofrio earned his PhD from Grenoble Alpes University in 2011 followed by a postdoctoral stay at Purdue University, where he also served as a Visiting Assistant Professor from 2012 to 2016. From 2016, Dr. Onofrio was an Assistant Professor at the Hong Kong Polytechnic University, where his research spanned atomistic simulations, material property optimization, and innovative computational techniques.
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