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Check out our FAQ page to find out more about
the IEEE Nanotechnology Council!
January 12th, 2022
January 12th, 2022
IEEE NTC Facebook website is linked below. It can also be linked to by the Facebook option at the upper right corner of the front page of the NTC website.
NTC officers, members, conference/workshop organizers are invited to join it and post relevant information.
Open website in which only authorized members are allowed to post articles:
http://www.facebook.com/groups/ieeenanotechnology/ (https://www.facebook.com/groups/550239578466583/)
January 12th, 2022
The NTC has several Linked-in sites:
Main NTC ‘company’ page: https://www.linkedin.com/company/ieee-ntc
NTC Women in Nanotechnology (WIN) ‘company’ page: https://linkedin.com/company/ieee-nanotechnology-council-women-in-nanotechnology
NTC Young Professionals (YP):
- Region 7: https://www.linkedin.com/company/ieee-ntc-yp-canada/
- Region 8: https://www.linkedin.com/company/ieee-ntc-young-professionals-r8
- Region 9: https://www.linkedin.com/company/ieee-ntc-yp-r9
- Region 10: https://www.linkedin.com/company/ieee-ntc-yp-r10-ap/
IEEE-NANO Conference: https://www.linkedin.com/company/ieee-nano-conferences
April 28th, 2025
All eligible students or student teams are invited to participate in the International Conference on Nanotechnology Student Design Competitions (SDCs). The competition encourages students to employ creative problem solving and gain practical design experience by developing small samples, synthesis and characterization methodologies,
novel software, simple prototypes or system to address a problem stated in the competition rules while following specified constraints.
Participants, Requirements & Rules:
- All full-time undergraduate (B.Sc.) and graduate students (M.Sc. & PhD) worldwide are invited to take part in the Nano SDC.
- These students must have an accepted paper to NANO 2025.
- Students can form groups of at least 1 member, up to a maximum of 4 members. All team members must be full-time students while working on the project. A student cannot be part of two groups.
- At least on team member must register to the NANO 2025 Conference and attend in person the NANO SDC to assist with presentation, showcase, measurements (where applicable) and answer to judges’ questions.
- To participate in NANO SDC it is necessary to compile a form using the link provided below.
- The deadline is the 30 April 2025.
- Three different topics are given, and students can select only one of the three topics. The students’ project may or may not be directly related to the submitted paper. In other words, if a student submitted a paper to IEEE NANO, he/she can participate to any topics of the Nano SDC if such a paper is accepted and registered, independently from the manuscript subject. The students would have time to work on a project to be presented for the NANO SDC until July 2025.
- Students are advised to contact the individual competition organizers as early as possible, to ensure a full understanding of the rules, design specifications and judging criteria before beginning their projects.
- The student must have an academic advisor and he/she/their must certify that the work is completely made by the students.
- The students must notify the Nano SDC organizers at least one week before the date of the competitions if they plan to withdraw or will not be able to participate in person.
- The NANO SDC will take place on July 2025 during a specific public session within the IEEE NANO 2025 Conference, during which they will have to show in 10-15 min their prototypes or software and demonstrate their design outcomes.
- Winners will be recognized during the Social Dinner of IEEE NANO2025. Winning teams are awarded with a certificate, recognized at the social dinner, and will have a chance to submit a paper to the IEEE Nanotechnology Magazine for a special session dedicated to the NANO SDC.
Disclaimer: Student competitors should be aware that the NANO2025 will not assist participants in getting necessary equipment or designed circuits/systems into the United States of America. Students are responsible for the specific instrumentation needed for the SDCs (e.g., laptop, circuit boards, etc.). The students will bring their designs (e.g., software, prototypes, etc.) to the competition where they perform simple measurements or showcase their results and compete against other student teams. There are different competitions spanning a wide range of topics. Links to descriptions and rules for each competition are below.
N.B.: Travel visas and shipping your project equipment are your responsibility; it is recommended to arrange these as early as possible.
Design Competition Topics
SDC1 – Nanomaterials for Innovative Sensors
SDC2 – Computational Tools & Apps for the Modeling and Design of Nanodevices
SDC3 – Educational Games & Tools for Nanotechnology
More information are available on the IEEE NANO 2025 Website.
Participation Link
To participate in the NANO SDC, click the link below and fill in the form. You will be asked to provide contact information for all team members and your academic advisor, and you will also need to upload a short abstract describing your design approach. In addition, your academic advisor must send an email to the organizers of the competition certifying
that the work is yours, not theirs. The application deadline is 30 April 2025.
Students are advised to contact the individual competition organizers as early as possible to ensure a full understanding of the design specifications and judging criteria before beginning their projects.
Click Here to Submit Your Application.
April 24th, 2025
The IEEE International Conference on Nanotechnology IEEE-NANO (https://2025.ieeenano.org/), the flagship conference of the IEEE Nanotechnology Council (IEEE NTC), will be held in Washington, D.C. on 13-16 July 2025. Continuing the initiative under the motto “An Extended Bridge to Latin America” and as part of the conference
activities related to the celebration of the 25th anniversary of IEEE-NANO, the organizing committee has planned a series of outreach activities dedicated to young professionals and researchers from Latin America (IEEE Region 9 or R9).
In this regard a R9 Tutorial Day is scheduled for 17 July. This event features four invited tutorial talks given by speakers originally from Region 9, covering special topics in Nanotechnology and Nanosciences. The R9 Tutorial Day will be held remotely, in a virtual environment, alongside regular conference activities in Washington D.C.
Participation is completely free of charge, with only a simple free pre-registration required (details will be announced later-on). The line-up of confirmed speakers, along with their general topics, is as follows (final titles will be announced shortly):
- Enrique Solano (Peru), Quantum Computing, CEO of the company Kipu-Quantum,
Berlin, Germany. https://scholar.google.com.br/citations?hl=en&user=0ZxS2k0AAAAJ - Marcello Pavanello (Brazil), Nanoelectronics, IEEE ED-S Distinguished Lecturer,
Centro Universitario FEI. https://scholar.google.com.br/citations?user=2iRk15MAAAAJ&hl=en - Monica Garcia (Argentina), Nanomedicine Applications, L’Oréal UNESCO 2023 award
recipient, National University of Cordoba (UNC),
https://scholar.google.com.br/citations?hl=en&user=CkFSDKMAAAAJ - Rodrigo Capaz (Brazil), Nanomaterials, Director, Brazilian Nanotechnology National
Laboratory, Federal University of Rio de Janeiro (UFRJ),
https://scholar.google.com.br/citations?user=2HZbMZsAAAAJ&hl=en
Participation is open to all IEEE-NANO 2025 conference attendees and all members of the
IEEE NTC community. We hope to see you there.
IEEE-NANO 2025
International Outreach Coordinator
Murilo A Romero (University of Sao Paulo, Brazil)
General Co-Chairs
Jim Spicer (Johns Hopkins University, USA)
Bonnie L. Gray (Simon Fraser Univ., Canada)
Xiaoning Jiang (North Carolina State University, USA)
Kremena Makasheva (CNRS, University of Toulouse, France)
April 24th, 2025
Since its founding in 2001, IEEE-NANO has been the flagship conference of the IEEE Nanotechnology Council (NTC). Its sustained support and promotion of advanced research in nanoscience and nanotechnology is unsurpassed in the technical community. Over the years, IEEE-NANO has been held around the globe in China, Germany, Japan, Canada, Spain, the United Kingdom, Italy, South Korea, Ireland, the United States, and online (we will never forget the COVID years) and has benefited from the efforts of countless volunteers. Their ongoing commitment to the NTC and to NANO has allowed our
community to share advancements and recognize accomplishments in nanotechnology.
At its beginning, IEEE-NANO was the forum where the current World Nanotechnology Leaders first reported their work and contributed to the development and visibility of many researchers all over the globe. The nanotechnology field has evolved with the times, but the spirit of the IEEE-NANO conference remains. It fosters research discovery,
technical innovation, and reduction to practice – the hallmarks of a vibrant technical community.
Please join us as we celebrate the history of this important conference at the 25th IEEE International Conference on Nanotechnology (IEEE-NANO 2025) in Washington, DC, USA, 13 – 16 July 2025.
Please contact us (spicer@jhu.edu) if you have precious moments from previous IEEE NANO conferences that you would like to share with us and with the nanotechnology community.
April 2nd, 2025
https://ieeenmdc.org/nmdc-2025
Download CFP (PDF)
IEEE NMDC is a flagship conference series of the IEEE Nanotechnology Council (NTC), focusing on research advances in the fields of nanoscience and nanotechnology.
The 20th IEEE Nanotechnology Materials and Devices Conference (NMDC 2025) will be held in New Delhi, India, October 12-15, 2025
Conference Scope:
The conference focuses on the latest scientific and technological advances related to
* Nanorobotics and nanomanufacturing
* Nano-biomedicine
* Nanofabrication
* Nano-Optics, Nanophotonics, and Nano-Optoelectronics
* Spintronics
* Nanoelectronics
* Nanosensors and Nanoactuators
* MEMS/NEMS
* Nanoelectronics
* Nano-fluidics and integrated bio-chips
* Nanomaterials
* Nanometrology and Characterization
* Modeling and Simulation
* Nanopackaging
* Nanomagnetics
* Nanoenergy, Environment and Safety
* Nano-acoustic Devices, Processes & Materials
* Quantum, Neuromorphic & Unconventional Computing
* Emerging Plasma Nanotechnologies
* Education in nanotechnology
* Ethics in Nanotechnology
* Commercializing nanotechnology
* Fundamentals and applications of nanotubes, nanowires, quantum dots and other low dimensional materials
Paper submission:
Submit abstracts and papers at https://nano.papercept.net/conferences/scripts/start.pl.
Be sure to select “NMDC’25”.
Accepted and presented full papers (4 to 6 pages) for IEEE-NMDC will be included in IEEE Xplore as well as other Abstracting & Indexing (A&I) databases.
Key Dates:
Abstract Submission: 31 May 2025
Full Paper Submission: 30 July 2025
Notification of Acceptance: 1 Sept 2025
Final Paper Submission: 1 October 2025
General Chair:
Prof. Kaushik Pal, Indian Institute of Technology, Roorkee, India
Technical Program Chair: Supriyo Bandyopadhyay, Virginia Commonwealth University, USA
Treasurer: Prof. Amalendu Pattanaik, Indian Institute of Technology, Roorkee, India
Publications Chair: Prof. Rohit Sharma, Indian Institute of Technology, Ropar, India
Publicity chair: Prof. Ankush Kumar, Indian Institute of Technology, Roorkee, India
Registration Chair: Prof. Rajesh Kumar Ulaganathan, Indian Institute of Technology, Roorkee, India
Tutorials Chair: Prof. M. Sankar, Indian Institute of Technology, Roorkee, India
Local arrangement chair: Prof. Indranil Lahiri, Indian Institute of Technology, Roorkee, India
Exhibits chair: Prof. Debrupa Lahiri, Indian Institute of Technology, Roorkee, India
Sponsor chair: Prof. M. Sankar, Indian Institute of Technology, Roorkee, India
Webmaster: Prof. Santanu Pradhan, Indian Institute of Technology, Roorkee, India
March 28th, 2025
The NTC Chapter and Regional Activity Committee is calling for Expressions of Interest for the role of Region 10 (India) Chapter Coordinator.
Anyone interested, please send your CV and a brief cover letter explaining your past involvement with NTC and why you are interested in the role to the Chapter and Regional Activity Committee Chair, Prof. Lan Fu (lan.fu@anu.edu.au).
March 27th, 2025
The IEEE Nanotechnology Council (NTC) is seeking nominations for the following elected positions.
(1) Election: VP-elect for Conferences (3-years: serves as elect in 2026; VP 2027-2028)
(2) Election: VP-elect for Finances (3-years: serves as elect in 2026; VP 2027-2028) [incumbent is eligible]
(3) Election: Member-at-Large (MAL) (up to 3) (2026-2027)
Unless otherwise noted, all positions are two-year terms and start Jan. 1, 2026. MAL can serve 4 consecutive years
Nominations should include a statement from the candidate and a bio in IEEE format.
The deadline for nominations is May 15, 2025.
A position description and nomination form can be downloaded here.
Duties for the positions are described in the NTC Constitution which can be found here, and in the NTC Bylaws which can be found here.
Eligibility: Officer candidates are nominated from current AdCom members or from those past members who have served as Member Society-appointed or ex-officio AdCom members within the previous five years. Review the AdCom roster at https://ieeenano.org/adcom/.
MAL candidates serve as members of the AdCom and are to provide the Council with independent insights and positions that are in support of the global nanotechnology community, especially those involved in independent research, development and commercialization, to represent the Council positions and statements as needed to these global constituencies and to complete the specific tasks identified in their candidacy documents. MAL are NOT required to be members of Member Societies.
NOTE: Nominations may be made only by AdCom members (Society representatives and ex-officio; see website AdCom roster).
Note: An individual may not serve concurrently as both a Council officer and a Council Member Society representative.
Submit nominations by midnight (PT) 15-May-2025.Use Google form or email to NTC Nominations Chair.
- NEW for 2025: Online Google nomination form: https://forms.gle/SDse2P7xFxqQ7Xdf7
- OR Email the nominations to Fabrizio Lombardi NTC Nominations Committee Chair at lombardi@coe.neu.edu
The election will be held at the NTC AdCom in Washington, DC USA on July 13, 2025.
Candidates are required to appear before the AdCom for the election, either in person or virtually.
March 19th, 2025
Virtual Workshop on “Next Generation Computing in the Era of Chiplets”
Date: April 2, 2025
Start Time: 9:30am (CDT)
Timezone – Central
Length/ Duration: 90 minutes
Kick Off – Moitreyee Mukherjee-Roy (IBM) TC19 Chair
Speaker 1 – Joshua Rubin (IBM)
Title – Memory challenges and solutions for chiplets
ABSTRACT – The AI hardware industry landscape is full of diverse approaches to hardware design, ranging from large SoCs to chipletized systems based on both 3D and 2.xD packaging. Even within the chipletized systems the chiplet architecture can vary greatly. Most current solutions are based on silicon designed by a single hardware vendor. In this workshop we will review the AI hardware industry landscape and compare the various approaches. Furthermore, we will explore a vision for disaggregation of IBM’s recently announced Spyre accelerator SoC, designed by IBM Research. We will look at how an AI chiplet in combination with other chiplets in an open chiplet ecosystem would enable creation of performant chiplet architectures for domain-specific applications.
Short BIO :
Joshua Rubin is a Senior Engineer at IBM, where he has been technical lead on projects dealing with wafer scale 3D integration, system performance analysis for novel technical elements, heterogeneous integration, and AI hardware design. An IBM Master Inventor, he holds over 90 patents in transistor design and integration, power distribution, 3D integration, packaging, and memory devices. He earned a PhD in electrical engineering at Cornell University. He has also published several technical articles and presented at several conferences including the Electronic Components and Technology Conference (ECTC), IEEE Journal of Solid-State Circuits (ISSCC), IEEE Electron Device Letters (EDL), and IEEE International Conference on MEMS. Most recently he was a technical lead for the packaging and card design of IBM’s latest Artificial Intelligence Unit (AIU) product.
Speaker 2 – Srikanth Rangarajan
Title: Advanced Thermal Management of Next-Generation of High-Performance Computing
Abstract: As high-performance computing (HPC) systems continue to evolve, the challenge of managing heat generated by increasingly powerful and compact electronic components has become paramount. This talk explores cutting-edge thermal management solutions that are paving the way for the next generation of HPC systems. We will discuss innovative approaches such as single- and two-phase liquid cooling. The presentation will also cover advancements in phase change materials for managing transient heat loads. Additionally, the talk will examine the integration of artificial intelligence and machine learning into thermal management systems, enabling real-time temperature monitoring and predictive analysis for optimal cooling strategies. The talk will highlight how these technologies are not only addressing current thermal challenges but also enabling the development of more powerful, efficient, and reliable HPC systems for the future.
Short BIO:
Srikanth Rangarajan currently works as an Assistant Professor in the School of System Science and Industrial Engineering at Binghamton University. He received his M.S & Ph.D. in Mechanical Engineering from the Indian Institute of Technology Madras 2017. His research interests include Energy Storage management systems, electronic packaging, Digital twinning for electronics and batteries, Thermal energy storage, Thermal Management of electronics, and Data center cooling. Srikanth has published 35 international journal articles so far. Srikanth is also the author of the book “Phase Change Material Heat Sinks: A multi-objective Perspective.”
Prior to joining the School of System Science and Industrial Engineering, Srikanth worked as an Associate Research Professor in the Department of Mechanical Engineering at SUNY Binghamton
Research Interests
- Thermal management, optimization, Digital Twinning and sustainability of electronic systems
- Advanced packaging and heterogeneous integration of electronic systems
- Data Center cooling
- Digital twinning and optimization of battery systems
- Thermal Energy Storage: Design and optimization
Speaker 3 – Si-Ping Gao:
Title – Power Delivery of Heterogeneous Integration: Challenges and Opportunities
As semiconductor design continues to evolve, chiplet technology has emerged as a promising solution to the limitations of traditional monolithic integrated circuits [1]. The shift towards chiplet-based heterogeneous integration (HI) offers flexibility, scalability, and improved manufacturing yields. However, this new approach presents significant challenges in power delivery. Efficient power delivery in HI systems is crucial to maintaining performance and reliability across multiple, independently manufactured and assembled die [2]. In this paper, we explore the key issues surrounding power delivery in HI architectures, including power integrity, voltage regulation, interconnect design, and thermal management [3]. We also propose innovative power delivery network (PDN) strategies tailored to the specific needs of chiplet designs. Our findings demonstrate how advanced PDN designs can mitigate power-related issues while supporting the energy efficiency, performance, and scalability demands of future semiconductor systems. This talk provides valuable insights for industry professionals and academics aiming to address the power delivery challenges inherent in the next generation of chiplet-based HI technologies.
References
[1] K. Radhakrishnan, M. Swaminathan, and B. K. Bhattacharyya, “Power Delivery for High-Performance Microprocessors – Challenges, Solutions, and Future Trends,” IEEE Trans. Compon. Packag. Manuf. Technol, vol. 11, no. 4, pp. 655–671, Apr. 2021.
[2] J. Kim et al., “Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse,” IEEE Trans. Very Large Scale Integr. Syst., vol. 28, no. 11, pp. 2424–2437, Nov. 2020.
[3] J. Kim et al., “Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs,” IEEE Trans. Compon. Packag. Manuf. Technol, vol. 11, no. 12, pp. 2148–2157, Dec. 2021.
Short Bio:
Si-Ping Gao (Senior Member, IEEE) received the B.Eng., M.Eng. and D.Eng. degrees in electronic engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2007, 2009, and 2013, respectively.
From 2013 to 2017, he was a Scientist with the Department of Electronics and Photonics, Institute of High Performance Computing (IHPC), A*STAR, Singapore. From 2017 to 2022, he was a Research Fellow in the Department of Electrical and Computer Engineering, National University of Singapore (NUS). From 2022 to 2024, he was a Senior Engineer of AMD. He is currently a Full Professor of NUAA. He has authored more than 100 refereed papers and one book chapter. He holds several patents. His research interests include EMC/EMI, signal and power integrity for 2.5D/3D ICs, and RFICs.
Dr. Gao received the Young Professional Award from the IEEE EMC Society in 2021 and many other technical awards including the APEMC 2016 Best Symposium Paper Award, the SPI 2017 Young Investigator Training Program Award, the URSI GASS 2017 Young Scientist Award, the Outstanding Young Scientist Award at the 2018 Joint IEEE EMC & APEMC Symposium, and the IEEE MTT-S IMWS-AMP 2020 Best Paper Award. He served as the TPC Chair and Co-chair of IEEE MTT-S IMWS-AMP 2025 and 2021, respectively, the Technical Paper Chair of APEMC 2022. He was a Distinguished Reviewer of IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY in 2023. He has been serving the IEEE EMC Singapore Chapter since 2016.
March 12th, 2025
Website URL: http://ieee-nanomed.org/2025/
Date: 1 – 4 December
Venue: Hong Kong, China
IEEE-NANOMED is one of the premier annual events organized by the IEEE Nanotechnology Council (NTC), and brings together physicians, scientists, and engineers from all over the world and every sector of academy and industry for the advancement of basic and clinical research in medical and biological sciences through nano/molecular medicine and engineering. Attendees of IEEE-NANOMED can share their latest research in engineering and nano/molecular medicine with other practitioners in their field and related fields, ranging from basic scientific and engineering research to translational and clinical research.
Important Dates:
Two-Page Abstract Deadline: 11 July 2025
Notification of Acceptance: 12 September 2025
Full Paper Deadline: 12 July 2025 (for best paper competition)
3 October 2025 (for inclusion in IEEE Xplore)
Early Bird Registration: 30 September 2025
March 5th, 2025
Date: May 20th, 2025
Time: 11:00AM Eastern Daylight Time (Montreal)
Title: Technology Computer-Aided Design and Ab Initio Simulations of Quantum-Technology Hardware
Speaker: Félix Beaudoin, Ph.D., Chief Executive Officer, Nanoacademic Technologies Inc.
Organizer: TC10 mentee member, Luiz Felipe Aguinsky
Register below to receive meeting link.
Abstract:
Quantum technologies are poised to revolutionize sensing, cryptography, and computing by leveraging the deepest quantum-mechanical effects such as quantum superposition and entanglement. However, quantum advantage relies upon quantum hardware such as superconducting qubits or spin qubits in semiconductors, which suffers from several defects and imperfections that may lead to decoherence. In addition, quantum-hardware design, prototyping, and characterization workflows that do not leverage mature and predictive technology computer-aided design (TCAD) simulation software often rely on excessive trial and error with real-world devices. This approach incurs high manufacturing and personnel cost and may even result in quantum devices that fail to meet performance requirements.
In this webinar, we describe how Nanoacademic Technologies’ ab initio (RESCU, NanoDCAL) and quantum TCAD (QTCAD®) software can be used for atomistic and TCAD modeling of quantum devices, akin to simulation and design workflows employed for standard semiconductor devices and materials. We will show how recent functional and performance advances in the QTCAD® software led to the demonstration of quantitatively predictive simulations of spin qubits in semiconductor gated quantum dots. In addition, we will describe how combining QTCAD® features with the large-scale density functional theory (DFT) software RESCU enabled calculating the addition energy of a single-phosphorus-donor spin qubit in silicon completely from first principles for a system containing more than 10,000 atoms. Finally, future applications of QTCAD®, RESCU, and NanoDCAL for superconducting-qubit device and materials modeling will be explored.
Bio:
Félix Beaudoin is the CEO of Nanoacademic Technologies Inc., a scientific software company based in Montréal, Québec, Canada. He first obtained an M. Sc. in theoretical physics from Université de Sherbrooke in 2011 under the supervision of Prof. Alexandre Blais, followed by a Ph.D. in theoretical physics from McGill University in 2016 with Prof. William A. Coish. In 2017-2018, Félix Beaudoin worked as a postdoctoral associate and university lecturer at Dartmouth College in the research group of Prof. Lorenza Viola, in close collaboration with the Quantum Information and Integrated Nanosystems Group led by Prof. William D. Oliver (Massachusetts Institute of Technology). Félix Beaudoin’s research background involves quantum-technology topics such as quantum noise, quantum control, quantum computing, quantum metrology, and modeling of spin qubits and superconducting qubits alike.
Félix Beaudoin joined Nanoacademic in 2019 as a Research Scientist and became the company’s Director of Quantum Technology in 2021. With a team of experts, he managed the development of Nanoacademic’s newest quantum modeling tool: QTCAD®. On January 1st, 2025, he was appointed CEO of Nanoacademic. In this capacity, his goal is to drive the company’s growth and product innovation in atomistic simulation and computer-aided design software, in addition to leading Nanoacademic’s strategic expansion in quantum technology.
Register for meeting link:
March 4th, 2025
The IEEE Nanotechnology Council is pleased to announce the appointments of Distinguished Lecturers for 2025.
| José Miguel García-Martín | 1. Nanostructured columnar thin films by magnetron sputtering: From fundamentals to devices |
| Deep Jariwala | 1. III-Nitride Ferroelectrics for Low-Power and Extreme Environment Electronics
2. Nanoscale Excitonic Semiconductors for Strong Light-Matter Interactions 3. Two-Dimensional Semiconductors for Low-Power Logic and Memory Devices |
| Davide Mencarelli | 1. Advanced modeling and design of RF devices and systems based on low-dimensional materials
2. Development of multi-physic and multi-scale models of electro/opto- mechanical systems forhigh-frequency devices 3. Rigorous numerical simulation of the combine quantum-electromagnetic problem for application to nonlinear device |
| Federico Rosei | 1. Multifunctional materials for emerging solar technologies 2D Conjugated Polymers: Organic Analogues of Graphene |
| Wenzhuo Wu | 1. Tellurene electronics and beyond |