Archive for the ‘Publication’ Category

CALL FOR PAPERS

 IEEE Open Journal of Nanotechnology (OJ-NANO)
Special Issue on
“In Tribute to Professor Brajesh Kumar Kaushik”

IEEE Open Journal of Nanotechnology (OJ-NANO), a gold fully open access journal launched in 2020 by the IEEE Nanotechnology Council, publishes research advancing the theory, design and development of nanotechnology and its scientific, engineering and industrial applications. The journal has an independent editorial board, an established peer-review process, is targeting a ten-week rapid publishing schedule and is fully compliant with funder mandates, including Plan S. Your work will be exposed to 5 million unique monthly users of the IEEE Xplore^® Digital Library. IEEE OJ-NANO received its first Journal Impact of 1.8 and is now indexed in the Science Citation Index Expanded (SCIE)^TM by Clarivate Analytics as well as in Scopus®! This development indicates increased visibility and profile for both the journal and its published articles, demonstrating IEEE OJ-NANO is a reliable and high-quality source of information in the field of nanotechnology.

IEEE OJ-NANO will devote a special issue to the memory of Prof. Brajesh Kumar Kaushik who passed away on July 31, 2024. Prof. Kaushik was the coordinator of the IEEE Nanotechnology Council chapters in India, a member of the Administrative Committee of the Council, and a guest editor of special issues on spintronics and neuromorphic computing in the IEEE Transactions on Nanotechnology and IEEE Transactions on Electron Devices. He was a member of the Technical Committee on Spintronics, and a Founding Member of the Technical Committee on Quantum, Neuromorphic and Unconventional Computing. He was an exemplary mentor to many students who are now active researchers in nanotechnology. His enthusiasm and compassion touched many in the nanotechnology community.

NOTE: IEEE OJ-NANO will waive the APC (Article Publishing Charge) for papers invited and accepted for publication in this special issue!

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“A call for papers is now open for the IEEE Journal on Exploratory Solid-State Computational Devices and Circuits special topic on “Energy-Efficient In-/Near-Memory Computing with Emerging Devices”.

Aims and Scope

AI models have continuously shown extraordinary performance in recent years for various applications including computer vision, natural language processing, large language models, etc. Accuracy-driven AI model architectures have largely increased the model sizes and computations at a very fast pace, especially demanding high-density memory storage. Frequent communication between the processing engine and the on-/off-chip memory leads to high energy consumption, which becomes a bottleneck for the AI hardware accelerator design.

To overcome such challenges, in-memory computing (IMC) and near-memory computing (NMC) have been presented as promising schemes for energy-efficient AI acceleration. The weights are stored in the memory cells and dot-product or other operations are performed within or near the memory array. Regarding the memory technologies for the IMC/NMC scheme, SRAM is mature but is volatile, consumes large area (e.g. 8T/10T bitcells) and suffers from the leakage power in the CMOS devices. Such disadvantages promoted the non-volatile memory (NVM) as an attractive solution for area-efficient IMC/NMC-based AI acceleration.

NVMs presented in the literature from both academia and industry include resistive random access memory (RRAM), phase change memory (PCM), spin-transfer-torque magnetic random access memory (STT-MRAM), ferroelectric field effect memory (FeRAM, FeFET), ferroelectric capacitive device, etc. Notably, the foundry companies including Intel, TSMC, Samsung, and Globalfoundries have commercialized or are prototyping monolithically integrated NVM technologies, e.g. RRAM, MRAM, FeRAM/FeFET, etc.

Compared to SRAM, NVM based IMC/NMC could provide bitcell array density benefits, but the peripheral circuits need to be considered together, and achieving higher energy-efficiency can be challenging due to high current consumption when turning on multiple low-resistance-state devices simultaneously. To address these concerns, new schemes for energy-efficient IMC/NMC with emerging NVM devices are being investigated and developed.

This special topic of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) is in line with such efforts and aims to call for paper submissions on the recent research advances in the area of the energy-efficient in-/near-memory computing spanning devices, circuits, and systems. Papers on the interaction and co-optimization of the materials and devices as well as circuits and architecture are solicited.

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IEEE Open Journal of Nanotechnology (OJ-NANO) Special Section on 

IEEE-NSENS 2024: Nano Materials and Devices for Sensors, AI, and Robotics

IEEE Open Journal of Nanotechnology (OJ-NANO), a gold fully open access journal launched in 2020 by IEEE Nanotechnology Council, publishes research advancing the theory, design and development of nanotechnology and its scientific, engineering and industrial applications. The journal has an independent editorial board, established peer-review process, is targeting a ten-week rapid publishing schedule and is fully compliant with funder mandates, including Plan S. Your work will be exposed to 5 million unique monthly users of the IEEE Xplore^® Digital Library. IEEE OJ-NANO received its first Journal Impact of 1.7 and is now indexed in the Science Citation Index Expanded (SCIE)^TM by Clarivate Analytics as well as in Scopus®! This development indicates increased visibility and profile for both the journal and its published articles, demonstrating IEEE OJ-NANO is a reliable and high-quality source of information in the field of nanotechnology.

IEEE OJ-NANO will devote a special section on “IEEE-NSENS 2024: Nano Materials and Devices for Sensors, AI, and Robotics” to a collection of papers highlighting research and technology development in the field of nanotechnology, particular of materials and devices for the applications in sensors, AI and robotics. IEEE Nanotechnology Council sponsors the 3^rd IEEE International Conference on Micro/Nano Sensors for AI, Healthcare, and Robotics (IEEE-NSENS 2024) held on 2 – 3 March 2024 to foster interaction between engineers, scientists and industry in these emerging areas.

IEEE OJ-NANO will devote a special section on “IEEE-NSENS 2024: Nano Materials and Devices for Sensors, AI, and Robotics” to a collection of papers highlighting research and technology development in the field of nanotechnology, particular of materials and devices for the applications in sensors, AI and robotics. IEEE Nanotechnology Council sponsors the 3^rd IEEE International Conference on Micro/Nano Sensors for AI, Healthcare, and Robotics (IEEE-NSENS 2024) held on 2 – 3 March 2024 to foster interaction between engineers, scientists and industry in these emerging areas.

NOTE: IEEE OJ-NANO will waive 25% of the APC (Article Publishing Charge) for papers accepted for publication in the NANOMED 2023 special issue!

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CALL for PAPERS

IEEE Open Journal of Nanotechnology (OJ-NANO)
Special Section on

Future Nanocomputing: Trends and Challenges

Guest editors

• Prof Giovanni Finocchio, Department of Mathematical and Computer Sciences, Physical Sciences and Earth Sciences, University of Messina, 98166, Messina, Italy, Email: giovanni.finocchio@unime.it
• Fabrizio Lombardi, College of Engineering, Northeastern University, Boston, MA, USA, Email: lombardi@ece.neu.edu
• Georgios Ch. Sirakoulis, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi, Greece, Email: gsirak@ee.duth.gr

Scope and purpose

The concept of nanocomputing refers to the ability of computers to represent and manipulate data in the nanometer scale. In practice, circuits and computer systems are constructed using transistors with channels significantly shorter than 100 nanometers. Consequently, the current objective is to develop computers that utilize devices no larger than 10 nanometers. To achieve this, nanocomputing must undertake a comprehensive examination of nanotechnology in the field of computing. This aspect comprises interdisciplinary investigations that traverse various fields through the utilization of nanoscale technologies and the exploration of innovative processing paradigms. At the lowest device level, it encompasses not only CMOS but also numerous emerging technologies (including spintronics, molecular, superconducting, and DNA). However, it also incorporates circuit design considerations. It is unsurprising that this research necessitates a forum (and related community) that transcends disciplines to deliberate on innovative post-CMOS and advanced technological avenues for nanocomputing. To address the primary challenges encountered by integrated electronics in the twenty-first century, inventive future resolutions are necessary.

This special issue will showcase the most recent advancements in the multidisciplinary domain of nanocomputing technologies. It will specifically highlight the most recent developments in the corresponding technologies that are applicable for the modeling, design, fabrication and testing of unconventional nanocomputing systems such as biological, quantum, spintronic, and neuromorphic systems. Notably, efficient fabrication and implementation frameworks (from circuits to modules) and a physical foundation (i.e., devices) are necessary for these technological paradigms to function so that computations at the nanoscale can be executed efficiently in such unconventional venues. Therefore, the scientific forum that is specifically focused on technologies for nanocomputing will feature contributions from eminent international theorists and experimentalists. This will offer a one-of-a-kind opportunity to discuss and exchange ideas, share knowledge, identify unresolved matters, and suggest avenues for future research in a vast array of disciplines, including material science, device physics, nonlinear circuit and system theory, memory, and computing applications (including computer architecture).

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Special Topic on 3D Logic and Memory for Energy Efficient Computing

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Guest Editors
Yu Cao, University of Minnesota, yucao@umn.edu
Jeff Zhang, Arizona State University, jeffzhang@asu.edu

Editor-in-Chief
Azad Naeemi, Georgia Institute of Technology, azad@gatech.edu

Aims and Scope

Monolithic microelectronic design is facing tremendous challenges in the growing need of computation memory bandwidth and latency, and the energy efficiency of computation which is limiting its performance and cost. Although recent advances (e.g., domain-specific acceleration, near-memory and in-memory computing techniques) try to address these issues, the scaling trend of monolithic design still lags behind the ever-increasing demand of AI algorithms, high-performance computing, high-definition sensing and other data-intensive applications. In this context, technological innovations, in particular 3D integration through packaging and monolithic methods, are critical to enabling heterogeneous integration (HI) and bringing significant performance, energy and cost benefits beyond traditional chip design. 3D logic and memory design allow heterogeneous functional macros (i.e. chiplets) to be flexibly produced and connected with higher interconnection density, length reduction and area utilization, opening new opportunities across the microelectronic design stack.

The paradigm shift to heterogeneous integration and monolithic 3D methods requires a tight collaboration between packaging and chiplet designs spanning the entire design cycle, including devices, circuits, architectures, and design automation tools. Logic and memory will be partitioned into various 3D modules. The designers need to customize each module and define the interface, and assess system-level tradeoffs in performance, data movement, and energy efficiency. Design and synthesis tools have to be aware of 3D integration and planning knowledge (e.g., power delivery, heat dissipation and reliability) to enable the packaging and chiplet co-design. Furthermore, early predictive modeling and analysis of the 3D HI circuits and systems are essential to minimize the iteration cost between 3D architecture definition and design implementation.

This special issue of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) aims to call for the recent research advances in the area of 3D logic and memory design spanning from monolithic 3D and advanced packaging technology to circuits and architectures. Papers on co-design and optimization across multiple domains are encouraged.

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 IEEE Open Journal of Nanotechnology (OJ-NANO)
Special Section on
“IEEE-NANOMED 2023: Nano/Molecular Medicine & Engineering”

IEEE Open Journal of Nanotechnology (OJ-NANO), a gold fully open access journal launched in 2020 by IEEE Nanotechnology Council, publishes research advancing the theory, design and development of nanotechnology and its scientific, engineering and industrial applications. The journal has an independent editorial board, established peer-review process, is targeting a ten-week rapid publishing schedule and is fully compliant with funder mandates, including Plan S. Your work will be exposed to 5 million unique monthly users of the IEEE Xplore^® Digital Library. IEEE OJ-NANO received its first Journal Impact of 1.7 and is now indexed in the Science Citation Index Expanded (SCIE)^TM by Clarivate Analytics as well as in Scopus®! This development indicates increased visibility and profile for both the journal and its published articles, demonstrating IEEE OJ-NANO is a reliable and high-quality source of information in the field of nanotechnology.

IEEE OJ-NANO will devote a special section on “IEEE-NANOMED 2023: Nano/Molecular Medicine and Engineering” to a collection of papers highlighting research and technology development in the field of nanobiotechnology, molecular engineering, micro/nano-fluidics, micro/nano-system integration, nano-biology and nanomedicine. IEEE Nanotechnology Council sponsors the 16^th IEEE International Conference on Nano/Molecular Medicine & Engineering (IEEE-NANOMED 2021) held on 5 – 8 December 2023 to foster interaction between physicians, scientists and engineers in these emerging areas.

NOTE: IEEE OJ-NANO will waive 25% of the APC (Article Publishing Charge) for papers accepted for publication in the NANOMED 2023 special issue!

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IEEE Open Journal of Nanotechnology (OJ-NANO) is proud to announce its first Journal Impact Factor of 1.7! Learn more about OJ-NANO and submit your article today: https://oj-nano.ieeenano.org/.

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Special Topic on Steep Slope Transistors for Energy-Efficient Computing & More

Guest Editor: Alan Seabaugh, University of Notre Dame, seabaugh.1@nd.edu
Editor-in-Chief: Azad Naeemi, Georgia Institute of Technology, azad@gatech.edu

Aims and Scope:

Tunnel field-effect transistors (FETs) and low-subthreshold-swing steep-slope (SS) transistors hold promise to outperform complementary metal-oxide semiconductor technology (CMOS) at low voltage and realize more energy-efficient logic for computation. The aim of this special topics issue is to highlight experimental advances and ideas that make SS transistors attractive for integration with CMOS to realize better power-performance logic. Aspirational characteristics for n- and p-type steep transistors can be summarized as follows: drain currents exceeding 200 μA/μm at a supply voltage below 0.4 V, with SS less than 60 mV/decade beginning near 1 μA/μm and spanning more than 4 decades. Papers describing theory and modeling of transistors which can meet and surpass these goals are of interest, as are papers which assess the full design stack from devices to circuits and architecture to applications to identify system bottlenecks and inform technology development for computing, communications, or other applications. Materials approaches are not restricted to silicon CMOS and can be based on any semiconductor technology and incorporate multiferroic or other performance boosters. New approaches based on three-dimensional integration, heterogeneous integration, processing, or insights from manufacturing are also within the scope of this issue to advance understanding and progress in SS transistors.

Topics of Interest:

• TFET and other steep slope transistors with path to outperform CMOS at low voltage
• Experimental progress
• Theory and modeling
• Si, III-V, III-N, two-dimensional semiconductors and heterojunctions
• Multiferroic and other material/device design approaches
• 3-D integration, heterogeneous integration, processing, manufacturing
• Full-stack design to inform technology development

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Transactions on Nanotechnology Editorial Board Members Call for Nominations

Transactions on Nanotechnology (T-NANO) is soliciting editorship nominations for joining its Editorial Board as Associate Editor (AE) or Senior Editor (SE).

Editors (Associate and Senior) must show technical expertise in nanotechnology and commitment to collegiately work within the T-NANO Editorial Board (EB) to oversees and secure an objective and smooth paper review process under the Nanotechnology Council framework.

SEs and AEs serve for 3 years and the appointments are not renewable without a separation period. In special cases, EB members may be asked to serve for an additional, 4th year. During the first months of their appointments, newly appointed SEs and AEs will closely work with the Editor in Chief and the journal administrator.

Nominations (self-nominations are accepted) of academia, Industry, and government representatives are welcome. To nominate someone else or yourself, please send nominee name, affiliation, a brief statement of research interests (including 5-10 keywords), and CV to Sorin Cotofana at s.d.cotofana@tudelft.nl by January 15, 2023.