Archive for the ‘Publications’ Category

Editor-in-Chief, IEEE Nanotechnology Magazine (INM)

Nomination/Application Deadline: July 31, 2025

The IEEE Nanotechnology Council (NTC) invites nominations and applications for the position of Editor-in-Chief (EiC) of the IEEE Nanotechnology Magazine (INM). The appointment is for a two-year term beginning January 1, 2026, and is renewable up to two additional terms for a maximum of six years of service.

INM serves as a premier forum for communicating both cutting-edge research and broader perspectives on nanotechnology trends, developments, and applications. It bridges academia, industry, and government, featuring accessible, high-impact content for a broad readership. The magazine includes tutorials, industry and education news, commercialization and policy features, opinion pieces, tools and techniques, and more. Most recently, INM was awarded its Impact Factor (2.3), marking a major milestone that underscores its growing visibility and potential as a leading voice in the nanotechnology community.

The new EiC will play a key leadership role in shaping the magazine’s content, vision, and reach at a pivotal point in its growth.

Candidate Qualifications:

• IEEE member in good standing.
• Prior editorial experience (e.g., EiC, Senior Editor, or Associate Editor), preferably with IEEE or NTC publications.
• Broad understanding of the academic, industrial, and governmental sectors related to nanotechnology.
• Proven leadership, organizational, and decision-making skills necessary to oversee the efficient manuscript review and publication process.
• Ability to engage a diverse set of contributors and readers.
• Participation in IEEE NTC activities is considered favorably.

Key Responsibilities:

• Defining and leading the magazine’s editorial strategy and vision.
• Appointing and managing a dynamic, diverse editorial board, with the concurrence of the NTC Executive Committee.
• Overseeing a rigorous and timely editorial process, with support from INM’s publications staff, while upholding the highest ethical standards.
• Ensuring the quality, relevance, and timeliness of published content, and leading the development of special issues and features to broaden INM’s reach and impact.
• Collaborating with NTC Technical Committees and leadership to align the magazine with the Council’s overall mission and priorities.

The Editor-in-Chief reports to the NTC Vice President for Publications, chairs the TNANO Editorial Board, and serves as a voting member of the NTC Publications Committee. The initial term of service will be from January 1, 2026 to December 31, 2027.

How to Apply or Nominate:

Submit nominations or applications to: Prof. Georgios Ch. Sirakoulis, NTC Vice President for Publications, via email at gsirak@ee.duth.gr.

Each nomination or application must include:

1. Full name and contact information of the candidate.
2. Name and contact information of the nominator (if applicable).
3. Full CV that includes:
   • A list of relevant publications.
   • Detailed editorial experience.
   • Any involvement in IEEE and NTC activities, including committee memberships, leadership roles, or other forms of service.
4. A statement of interest (up to 500 words) outlining the candidate’s editorial vision and proposed course of action for the magazine, including:
5. • Vision and strategic direction for INM.
   • Opportunities for growth and engagement.
   • Editorial milestones and timelines for achieving them
   • Proposed editorial structure or team to support implementation
6. (Optional) A brief supporting statement from the nominator(s).

Nomination/Application Deadline: July 31, 2025

 Submit nomination or application to:

Georgios Ch. Sirakoulis, NTC Vice President for Publications, via email at gsirak@ee.duth.gr.

Editor-in-Chief, IEEE Transactions on Nanotechnology (TNANO)

Nomination/Application Deadline: July 31, 2025

The IEEE Nanotechnology Council (NTC) invites nominations and applications for the position of Editor-in-Chief (EiC) of the IEEE Transactions on Nanotechnology (TNANO). The appointment is for a two-year term beginning January 1, 2026, and is renewable up to two additional terms for a maximum of six years of service.

TNANO publishes high-impact research of lasting value in the rapidly advancing field of nanotechnology – one of today’s most dynamic and transformative frontiers in science and industry. As breakthroughs continue to shape the future of technology, TNANO remains committed to serving as a leading platform for disseminating cutting-edge discoveries and developments. Recognizing the evolving nature of the field, the journal periodically revises its scope to reflect emerging trends and real-world advances.

This EiC role presents a unique opportunity to shape the journal’s editorial direction, build an exceptional editorial board, and lead the publication through its next phase of growth and impact.

Candidate Qualifications:

• IEEE member in good standing.
• Prior editorial experience (e.g., EiC, Senior Editor, or Associate Editor) in an archival journal or magazine, preferably with IEEE or NTC.
• Strong familiarity with nanotechnology across academia, industry, and government.
• Proven leadership, organizational, and decision-making skills necessary to oversee the efficient manuscript review and publication process.
• Ability to attract, inspire, and lead a high-caliber editorial board.
• Participation in IEEE NTC activities is a plus.

Key Responsibilities:

• Actively soliciting and promoting high-quality manuscript submissions.
• Appointing and leading a diverse, dynamic editorial board, with the concurrence of the NTC Executive Committee.
• Managing a rigorous and timely editorial process and upholding the highest ethical standards.
• Promoting the journal’s strategic growth through special issues and new initiatives.
• Resolving editorial conflicts as necessary and maintaining transparency throughout the publication process.

The Editor-in-Chief reports to the NTC Vice President for Publications, chairs the TNANO Editorial Board, and serves as a voting member of the NTC Publications Committee. The initial term of service will be from January 1, 2026 to December 31, 2027.

How to Apply or Nominate:

Submit nominations or applications to: Prof. Jin-Woo Kim, NTC President, via email at jwkim@uark.edu
Each nomination or application must include:

1. Full name and contact information of the candidate.
2. Name and contact information of the nominator (if applicable).
3. Full CV that includes:
   • A list of relevant publications.
   • Detailed editorial experience.
   • Any involvement in IEEE and NTC activities, including committee memberships, leadership roles, or other forms of service.
4. A statement of interest (up to 500 words) outlining the candidate’s editorial vision and proposed course of action for the journal, including:
   • The candidate’s perspective on the current state of the publication, including key challenges and opportunities.
   • Proposed strategies and actions the EiC would take to address those challenges and seize opportunities.
   • Specific, measurable milestones and a timeline for achieving them.
   • A proposed editorial structure or team to execute the plan.
5. (Optional) A brief supporting statement from the nominator(s).

Nomination/Application Deadline: July 31, 2025

Submit nomination or application to:

Jin-Woo Kim, NTC President, via email at jwkim@uark.edu.

All authors of accepted NANO 2025 papers are invited to submit an extended version of their conference paper, for possible publication in IEEE Transactions on Nanotechnology.

The nanotechnology revolution is founded upon the understanding of phenomena occurring at the nanoscale and the ability to fabricate and manipulate nanomaterials and nanodevices for practical applications. Researchers are contributing new ideas from a wide range of disciplines, including materials science, biology, biomedicine, engineering, physics, and chemistry. To make interesting research presented at the 25^th IEEE International Conference on Nanotechnology (IEEE NANO 2025) widely available, in expanded form and in one publication, IEEE Transactions on Nanotechnology (TNANO) is extending a Call for Papers for a Special Section reflecting the scope of the conference.

When submitting an extended version of an IEEE NANO 2025 paper, authors are requested to significantly expand the conference version to contain substantial new technical material. Clear new contribution requirements, as per TNANO and IEEE restrictions on duplicated publications and the competitive acceptance process, of at least 50%, of novelty material in terms of new ideas and new results should be followed. The IEEE NANO 2025 paper has to be properly cited.

Submitted manuscripts will undergo a full journal peer review process. Submissions are open to all IEEE NANO 2025 participants and to other authors with an interest in the conference topics. The paper submission will be done via the IEEE author portal during the NANO2025 Special Section submission open window, with specific dates given below.

Submissions that reflect the Conference Scope and current state of the field are welcome in areas including but not limited to:

• AI in Nanotechnology
• Emerging Plasma Nanotechnologies
• Heterogenous Integration and Chiplets
• Modeling and Simulation
• Nano-Acoustic Devices, Processes, and Materials
• Nano-Biomedicine
• Nanoelectronics
• Nano-Energy, Environment, and Safety
• Nanofabrication
• Nanomagnetics
• Nanomaterials
• Nano-Metrology and Characterization
• Nano-Optics, Nanophotonics, and Nano-Optoelectronics
• Nanopackaging
• Nanorobotics and Nanomanufacturing
• Nanoscale Communications
• Nanosensors and Nanoactuators
• Nanotechnology for Soft Electronics
• Quantum, Neuromorphic, and Unconventional Computing
• Spintronics

Manuscripts for the TNANO Special Section must be submitted on-line using the IEEE TNANO manuscript template. Follow the guideline (Author Info – IEEE TNANO), and submit your paper via IEEE Author Portal (https://ieee.atyponrex.com/journal/tnano), indicating in the cover letter that you wish the paper to be considered for “IEEE Transactions on Nanotechnology (TNANO) Special Section on the “25^th IEEE International Conference on Nanotechnology (IEEE NANO 2025)” but also providing all the requested info related with the substantial new technical material included in the submitted manuscript when compared with the conference article.

Please note that the type of submissions is Regular Manuscripts, i.e., 4 to 6 pages in the two-column IEEE format, which includes figures, tables, and references. On submission to TNANO, authors should select the “Special Issue” manuscript type instead of “Regular Paper”.

Manuscripts will be subject to the standard competitive and constructive peer-review TNANO criteria with no article publishing charges. Accepted papers are published on the web in IEEE Xplore as soon as they are submitted in final form. Web-published papers have a DOI (Digital Object Identifier) and are fully citable and downloadable.

Important Dates

• Submission opening: October 1, 2025
• Submission deadline: November 31, 2025
• First decision (accept/reject/revise): January 31, 2026
• Revised papers submission: February 28, 2025
• Final decision: March 30, 2026

Guest Editors

• Francesca Urban, Drexel University, Philadelphia (PA) USA
  E-mail: fu36@drexel.edu
• Aniello Pelella, University of Roma Tor Vergata, Roma, Italy
  E-mail: aniello.pelella@uniroma2.it
• Antonio Di Bartolomeo, University of Salerno, Fisciano, Italy, E-mail: adibartolomeo@unisa.it

Editorial Board

• Sorin Cotofana (Editor in-chief), Delft University of Technology, Delft, The Netherlands

E-mail: S.D.Cotofana@tudelft.nl

• Giorgios Sirakoulis (Senior Editor), Democritus University of Thrace, Komotini, Greece

E-mail: gsirak@ee.duth.gr

• Malgorzata Chrzanowska-Jeske (Associate Editor), Portland State University, Portland (OR) USA

E-mail: h8mj@pdx.edu

Special Topic on Challenges and Opportunities for Information Processing and Storage with Ferroelectric Devices and Circuits

Guest Editor
Sourav Dutta, The University of Texas at Dallas, sourav.dutta@utdallas.edu

Editor-in-Chief
Azad Naeemi, Georgia Institute of Technology, azad@gatech.edu

Aims and Scope

The continued scaling of CMOS has been one of the key drivers towards the progress of modern computing. Miniaturization of advanced logic and memory has allowed us to achieve higher performance, reduced power consumption, and increased storage capacity. As the industry approaches the physical limits of conventional silicon scaling, new materials and devices need to be explored to continue this trend. Furthermore, new forms of computing need to be explored for making breakthrough advancements in hardware accelerator designs that can support the ever-growing size and complexity of the AI models.

Ferroelectric materials, with their unique property of spontaneous polarization that can be reversed by an external electric field, are promising candidates that can augment or replace conventional silicon-based semiconductor devices and act as scaling boosters for memory technology and enable new forms of information processing. For example, ferroelectric materials naturally exhibit non-volatile memory characteristics making them ideal candidates for memory application. By integration ferroelectric materials in the gate stack of a conventional silicon transistor, as an integrated capacitor with an access transistor and as a replacement for conventional charge-trap layers, new memory technologies in the form of ferroelectric field-effect transistor (FeFET), ferroelectric random-access memory (FeRAM) and ferroelectric NAND flash (Fe-NAND) can be realized. These can in turn enable orders of magnitude improvement in the storage capacity, energy-efficiency and latency for cache, DRAM and flash memories. Beyond conventional memories, ferroelectric devices also exhibit unique properties including multilevel polarization states and temporal dynamics, making them suitable for mimicking biological neural networks. As such, building digital, analog or mixed-signal circuits with ferroelectric devices can offer potential breakthroughs in energy-efficient, brain-inspired computing, overcoming the bottleneck of traditional von Neumann computing.

Such promising opportunities also come with practical challenges pertaining to choice of materials, scalability, performance, reliability and integration with CMOS. For example, aggressive scaling of ferroelectric materials for compatibility with advanced CMOS nodes can degrade their inherent ferroelectric behavior. Ferroelectric materials and devices suffer from fatigue, imprint, and retention issues, which can affect their long-term performance and reliability. Achieving high-speed switching comparable to SRAM remains a significant challenge. Finally, conformal deposition of ferroelectric materials with uniform properties across high aspect ratio 3-D structures is challenging, particularly for highly integrated devices.

This special issue of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) aims to call for the recent research advances that address both the challenges and opportunities for information processing and storage with ferroelectric devices and circuits. Papers on co-design and optimization across multiple domains including materials, devices, circuits and architecture/systems are encouraged.

Topics of Interests

Prospective authors are invited to submit original works and/or extended works based on conference presentations on various aspects of information processing and storage with ferroelectric devices and circuits. Topics of special interest include but are not limited to:

• Advancements in ferroelectric materials and devices addressing key challenges
• Across-the-stack co-design and optimization approaches from materials and device to application.
• Monolithic and/or heterogeneous 3D integration with CMOS.
• New digital, analog and mixed-signal circuit design including peripherals for energy-efficient information processing and high-density storage.
• Architectural-level design for energy-efficient information processing and high-density storage.
• Application-level advancements for energy-efficient information processing and high-density storage.

Important Dates
Open for Submission: Feb. 15, 2025
Submission Deadline: May 15, 2025
First Notification: June 15, 2025
Revision Submission: July 1, 2025
Final Decision: July 15, 2025
Publication Online: Aug. 1, 2025

Please refer to the JxCDC website for submission guidelines.

“A call for papers is now open for the IEEE Journal on Exploratory Solid-State Computational Devices and Circuits special topic on “Energy-Efficient In-/Near-Memory Computing with Emerging Devices”.

Aims and Scope

AI models have continuously shown extraordinary performance in recent years for various applications including computer vision, natural language processing, large language models, etc. Accuracy-driven AI model architectures have largely increased the model sizes and computations at a very fast pace, especially demanding high-density memory storage. Frequent communication between the processing engine and the on-/off-chip memory leads to high energy consumption, which becomes a bottleneck for the AI hardware accelerator design.

To overcome such challenges, in-memory computing (IMC) and near-memory computing (NMC) have been presented as promising schemes for energy-efficient AI acceleration. The weights are stored in the memory cells and dot-product or other operations are performed within or near the memory array. Regarding the memory technologies for the IMC/NMC scheme, SRAM is mature but is volatile, consumes large area (e.g. 8T/10T bitcells) and suffers from the leakage power in the CMOS devices. Such disadvantages promoted the non-volatile memory (NVM) as an attractive solution for area-efficient IMC/NMC-based AI acceleration.

NVMs presented in the literature from both academia and industry include resistive random access memory (RRAM), phase change memory (PCM), spin-transfer-torque magnetic random access memory (STT-MRAM), ferroelectric field effect memory (FeRAM, FeFET), ferroelectric capacitive device, etc. Notably, the foundry companies including Intel, TSMC, Samsung, and Globalfoundries have commercialized or are prototyping monolithically integrated NVM technologies, e.g. RRAM, MRAM, FeRAM/FeFET, etc.

Compared to SRAM, NVM based IMC/NMC could provide bitcell array density benefits, but the peripheral circuits need to be considered together, and achieving higher energy-efficiency can be challenging due to high current consumption when turning on multiple low-resistance-state devices simultaneously. To address these concerns, new schemes for energy-efficient IMC/NMC with emerging NVM devices are being investigated and developed.

This special topic of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) is in line with such efforts and aims to call for paper submissions on the recent research advances in the area of the energy-efficient in-/near-memory computing spanning devices, circuits, and systems. Papers on the interaction and co-optimization of the materials and devices as well as circuits and architecture are solicited.

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Special Topic on 3D Logic and Memory for Energy Efficient Computing

CALL FOR PAPERS

Guest Editors
Yu Cao, University of Minnesota, yucao@umn.edu
Jeff Zhang, Arizona State University, jeffzhang@asu.edu

Editor-in-Chief
Azad Naeemi, Georgia Institute of Technology, azad@gatech.edu

Aims and Scope

Monolithic microelectronic design is facing tremendous challenges in the growing need of computation memory bandwidth and latency, and the energy efficiency of computation which is limiting its performance and cost. Although recent advances (e.g., domain-specific acceleration, near-memory and in-memory computing techniques) try to address these issues, the scaling trend of monolithic design still lags behind the ever-increasing demand of AI algorithms, high-performance computing, high-definition sensing and other data-intensive applications. In this context, technological innovations, in particular 3D integration through packaging and monolithic methods, are critical to enabling heterogeneous integration (HI) and bringing significant performance, energy and cost benefits beyond traditional chip design. 3D logic and memory design allow heterogeneous functional macros (i.e. chiplets) to be flexibly produced and connected with higher interconnection density, length reduction and area utilization, opening new opportunities across the microelectronic design stack.

The paradigm shift to heterogeneous integration and monolithic 3D methods requires a tight collaboration between packaging and chiplet designs spanning the entire design cycle, including devices, circuits, architectures, and design automation tools. Logic and memory will be partitioned into various 3D modules. The designers need to customize each module and define the interface, and assess system-level tradeoffs in performance, data movement, and energy efficiency. Design and synthesis tools have to be aware of 3D integration and planning knowledge (e.g., power delivery, heat dissipation and reliability) to enable the packaging and chiplet co-design. Furthermore, early predictive modeling and analysis of the 3D HI circuits and systems are essential to minimize the iteration cost between 3D architecture definition and design implementation.

This special issue of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) aims to call for the recent research advances in the area of 3D logic and memory design spanning from monolithic 3D and advanced packaging technology to circuits and architectures. Papers on co-design and optimization across multiple domains are encouraged.

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