IEEE Nanotechnology Council
Advancing Nanotech for Humanity


May 7, 2015 – Majority logic gate for 3D nano-scale magnetic computing

Irina Eichwald et al. demonstrated the potential of 3D high integration density digital computing based on physically field interacting nanometer-scaled magnets with a bistable magnetization state, representing the Boolean logic states ‘0’ and ‘1’, arranged in a 3D manner. Read the original article: Irina Eichwald et al 2014 Nanotechnology 25 335202 doi:10.1088/0957-4484/25/33/335202

3D NML computing - Nanotechnology 2014

Schematic of a 3D NML logic system. Logic computing is performed by 3D NAND/NOR gates. Information between functional layers is transmitted by magnetic vias, enabling magnetic signal crossing and computing on a multi-level regime. Electrical in and output sensors enable us to transform magnetic information into the electrical domain and vice versa.

(Posted by Yonhua Tzeng)

May 4, 2015 – Wafer-Level Hysteresis-Free Resonant Carbon Nanotube Transistors

Wafer-level integration of resonant-body carbon nanotube (CNT) field-effect transistors (FETs) of >1M CNTFETs/cmwith the resonance frequency tunable in situ by both a lateral gate and the back gate has been demonstrated by Ji Cao et al. offering promise in radio frequency signal processing and ultrasensitive sensing.

resonant cnt transistors - ACS Nano 2015

Adapted with permission from ACS Nano, 2015, 9 (3), pp 2836–2842 DOI: 10.1021/nn506817y. Copyright © 2015 American Chemical Society.  (Posted by Yonhua Tzeng)

May 1, 2015 – Fluorinated Epitaxial Graphene Diffusion Barrier on Germanium Enables Ge-MOSFET without Unstable Germanium Oxide

Zheng et al. demonstrated Ge-MOSFET with negligible C−V hysteresis, extremely low leakage, and superior equivalent oxide thickness by the aid of a fluorinated epitaxial graphene on Ge as an oxygen diffusion barrier to successfully prevent the formation of unstable germanium oxide between the Ge channel and the HfO2 gate oxide.  Read the original article: Xiaohu Zheng et al., Adv. Funct. Mater. 2015, 25, 1805–1813 (Posted by Yonhua Tzeng)

F-Gr on Ge as Diffusion Barrier

a) Schematic diagram showing the implementation of FGra as the diffusion barrier layer between the Ge substrate and HfO 2 dielectric layer in the Ge-based MOS device: (step 1) direct growth of continuous monolayer graphene on Ge; (step 2) FGra synthesized by exposure to SF 6 plasma; (step 3) dielectric deposition on FGra/Ge by atomic layer deposition; (step 4) MOS device completed by standard semiconductor manufacturing processes. b) Cross-sectional high-resolution TEM of the gate stack showing the absence of interfacial oxide formation in the presence of FGra and schematic diagram showing retarded diffusion in the vicinity of high- k /Ge interface.  (Credit Xiaohu Zheng et al., Adv. Funct. Mater. 2015, 25, 1805–1813 with permission)

April 29, 2015 – Subwavelength-scale Photoreduced Graphene Oxides Enable Holographic Images

Xiangping Li et al. demonstrated write-once holograms for wide-angle and full-colour three-dimensional images using subwavelength-scale pulsed femtosecond laser reduction of graphene oxide to enable multilevel optical index modulation and restoration of  vectorial wavefronts of polarization discernible images through the vectorial diffraction of a reconstruction beam. Read the original article: Li et al., Nature Communication  (2015) (Posted by Y. Tzeng)

ncomms7984-f1 - Graphene oxide for hologram - Nature Comm 2015