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SSCS Webinar Series – Professional Development Networking, and Career Growth
JxCDC SSCS Open Journal Webinar: Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures
Date: 6 February 2025
Time: 2:00 pm – 4:00 pm EST
Location: Webinar – Online
Contact: Aeisha VanBuskirk – a.vanbuskirk@ieee.org
Title: Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures
Abstract: Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. To understand the reasons underlying this trend, we develop a behavioral model of resistive IMCs to analyze the signal-to-noise-plus-distortion ratio (SNDR) of MRAM, ReRAM, and FeFET-based IMCs, employing parameter variation and noise models which are validated w.r.t. measured results from a recent MRAM-based IMC prototype in a 22nm process.
Presenters:
Saion K. Roy Saion K. Roy (Member, IEEE) received his Ph.D. from the University of Illinois at Urbana–Champaign, USA, in 2024, and his B.Tech. and M.Tech. degrees from the Indian Institute of Technology Kharagpur, India, in 2018.
Naresh R. Shanbhag Naresh R. Shanbhag (Fellow, IEEE) received the Ph.D. degree in electrical engineering from the University of Minnesota, Minneapolis, MN, USA, in 1993. He is currently the Jack Kilby Professor of Electrical and Computer Engineering with the University of Illinois at Urbana-Champaign, Champaign, IL, USA.
The IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC) is sponsored by:
IEEE Solid-State Circuits Society
IEEE Magnetics Society
IEEE Circuits and Systems Society
IEEE Electron Devices Society
IEEE Council of Electronic Design Automation
IEEE Council on Superconductivity
IEEE Nanotechnology Council