IEEE Nanotechnology Council
Advancing Nanotech for Humanity
IEEE

Heterogenous Integration and Chiplets TC

Heterogenous Integration and Chiplets TC 19

The scope of this TC is to serve as an interdisciplinary guide for scientists working in Semiconductor Packaging Process, Equipment, materials, substrates, Design, and EDA with the main goal to bring researchers of these different communities to create a common language and ecosystem for chiplets.

 

Topics of Interest

2.5D and 3D integration, interposer-based integration, die to wafer, wafer to wafer and die-to-die bonding, Chiplet Design, thermal management, power delivery, signal integrity, software/hardware co-design, System Technology Co-optimization (STCO). CPUs, GPUs, networking chips, AI accelerators.

 

Main Objectives of Technical Committee

Promotion of technological innovation and excellence in chiplet and the ecosystem surrounding chiplets such as substrate, equipment, materials, Design, EDA for facing societal challenges through participations in NTC conferences, publications and other outreach and education activities. Moreover, we also emphasis on global collaborations, inclusion, and diversity.

Leadership
Chair
Moitreyee Mukherjee-Roy IBM Research, USA mukherjm@us.ibm.com
Co-Chair
Giovanni Finocchio Univ.of Messina, Italy giovanni.finocchio@unime.it
Members
Pedram Khalili Amiri Northwestern University, USA pedram@northwestern.edu
Surya Bhattacharya Institute Of Microelectronics, Singapore bhattass@ime.a-star.edu.sg
 Nilesh Badwe IIT Kanpur, India nbadwe@iitk.ac.in
Isabel Desouza IBM, Bromont, Canada idesousa@ca.ibm.com
 Fernanda Kastensmidt Universidade Federal do Rio Grande do Sul – Brasil fglima@inf.ufrgs.br
Weiqiang Liu Nanjing University of Aeronautics and Astronautics, Nanjing liuweiqiang@nuaa.edu.cn
Prabhakar Subrahmanyam Technical Lead & Sr. Staff Thermal Architect, Intel prabhakar.subrahmanyam@intel.com