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IEEE Open Journal of Nanotechnology (OJ-NANO) Special Section on 

IEEE-NSENS 2024: Nano Materials and Devices for Sensors, AI, and Robotics

IEEE Open Journal of Nanotechnology (OJ-NANO), a gold fully open access journal launched in 2020 by IEEE Nanotechnology Council, publishes research advancing the theory, design and development of nanotechnology and its scientific, engineering and industrial applications. The journal has an independent editorial board, established peer-review process, is targeting a ten-week rapid publishing schedule and is fully compliant with funder mandates, including Plan S. Your work will be exposed to 5 million unique monthly users of the IEEE Xplore^® Digital Library. IEEE OJ-NANO received its first Journal Impact of 1.7 and is now indexed in the Science Citation Index Expanded (SCIE)^TM by Clarivate Analytics as well as in Scopus®! This development indicates increased visibility and profile for both the journal and its published articles, demonstrating IEEE OJ-NANO is a reliable and high-quality source of information in the field of nanotechnology.

IEEE OJ-NANO will devote a special section on “IEEE-NSENS 2024: Nano Materials and Devices for Sensors, AI, and Robotics” to a collection of papers highlighting research and technology development in the field of nanotechnology, particular of materials and devices for the applications in sensors, AI and robotics. IEEE Nanotechnology Council sponsors the 3^rd IEEE International Conference on Micro/Nano Sensors for AI, Healthcare, and Robotics (IEEE-NSENS 2024) held on 2 – 3 March 2024 to foster interaction between engineers, scientists and industry in these emerging areas.

IEEE OJ-NANO will devote a special section on “IEEE-NSENS 2024: Nano Materials and Devices for Sensors, AI, and Robotics” to a collection of papers highlighting research and technology development in the field of nanotechnology, particular of materials and devices for the applications in sensors, AI and robotics. IEEE Nanotechnology Council sponsors the 3^rd IEEE International Conference on Micro/Nano Sensors for AI, Healthcare, and Robotics (IEEE-NSENS 2024) held on 2 – 3 March 2024 to foster interaction between engineers, scientists and industry in these emerging areas.

NOTE: IEEE OJ-NANO will waive 25% of the APC (Article Publishing Charge) for papers accepted for publication in the NANOMED 2023 special issue!

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IEEE Open Journal of Nanotechnology (OJ-NANO)
Special Section on

Future Nanocomputing: Trends and Challenges

Guest editors

• Prof Giovanni Finocchio, Department of Mathematical and Computer Sciences, Physical Sciences and Earth Sciences, University of Messina, 98166, Messina, Italy, Email: giovanni.finocchio@unime.it
• Fabrizio Lombardi, College of Engineering, Northeastern University, Boston, MA, USA, Email: lombardi@ece.neu.edu
• Georgios Ch. Sirakoulis, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi, Greece, Email: gsirak@ee.duth.gr

Scope and purpose

The concept of nanocomputing refers to the ability of computers to represent and manipulate data in the nanometer scale. In practice, circuits and computer systems are constructed using transistors with channels significantly shorter than 100 nanometers. Consequently, the current objective is to develop computers that utilize devices no larger than 10 nanometers. To achieve this, nanocomputing must undertake a comprehensive examination of nanotechnology in the field of computing. This aspect comprises interdisciplinary investigations that traverse various fields through the utilization of nanoscale technologies and the exploration of innovative processing paradigms. At the lowest device level, it encompasses not only CMOS but also numerous emerging technologies (including spintronics, molecular, superconducting, and DNA). However, it also incorporates circuit design considerations. It is unsurprising that this research necessitates a forum (and related community) that transcends disciplines to deliberate on innovative post-CMOS and advanced technological avenues for nanocomputing. To address the primary challenges encountered by integrated electronics in the twenty-first century, inventive future resolutions are necessary.

This special issue will showcase the most recent advancements in the multidisciplinary domain of nanocomputing technologies. It will specifically highlight the most recent developments in the corresponding technologies that are applicable for the modeling, design, fabrication and testing of unconventional nanocomputing systems such as biological, quantum, spintronic, and neuromorphic systems. Notably, efficient fabrication and implementation frameworks (from circuits to modules) and a physical foundation (i.e., devices) are necessary for these technological paradigms to function so that computations at the nanoscale can be executed efficiently in such unconventional venues. Therefore, the scientific forum that is specifically focused on technologies for nanocomputing will feature contributions from eminent international theorists and experimentalists. This will offer a one-of-a-kind opportunity to discuss and exchange ideas, share knowledge, identify unresolved matters, and suggest avenues for future research in a vast array of disciplines, including material science, device physics, nonlinear circuit and system theory, memory, and computing applications (including computer architecture).

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Special Topic on 3D Logic and Memory for Energy Efficient Computing

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Guest Editors
Yu Cao, University of Minnesota, yucao@umn.edu
Jeff Zhang, Arizona State University, jeffzhang@asu.edu

Editor-in-Chief
Azad Naeemi, Georgia Institute of Technology, azad@gatech.edu

Aims and Scope

Monolithic microelectronic design is facing tremendous challenges in the growing need of computation memory bandwidth and latency, and the energy efficiency of computation which is limiting its performance and cost. Although recent advances (e.g., domain-specific acceleration, near-memory and in-memory computing techniques) try to address these issues, the scaling trend of monolithic design still lags behind the ever-increasing demand of AI algorithms, high-performance computing, high-definition sensing and other data-intensive applications. In this context, technological innovations, in particular 3D integration through packaging and monolithic methods, are critical to enabling heterogeneous integration (HI) and bringing significant performance, energy and cost benefits beyond traditional chip design. 3D logic and memory design allow heterogeneous functional macros (i.e. chiplets) to be flexibly produced and connected with higher interconnection density, length reduction and area utilization, opening new opportunities across the microelectronic design stack.

The paradigm shift to heterogeneous integration and monolithic 3D methods requires a tight collaboration between packaging and chiplet designs spanning the entire design cycle, including devices, circuits, architectures, and design automation tools. Logic and memory will be partitioned into various 3D modules. The designers need to customize each module and define the interface, and assess system-level tradeoffs in performance, data movement, and energy efficiency. Design and synthesis tools have to be aware of 3D integration and planning knowledge (e.g., power delivery, heat dissipation and reliability) to enable the packaging and chiplet co-design. Furthermore, early predictive modeling and analysis of the 3D HI circuits and systems are essential to minimize the iteration cost between 3D architecture definition and design implementation.

This special issue of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) aims to call for the recent research advances in the area of 3D logic and memory design spanning from monolithic 3D and advanced packaging technology to circuits and architectures. Papers on co-design and optimization across multiple domains are encouraged.

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