IEEE NTC 2026 TC 19 Heterogenous Integration and Chiplets September Webinar

Title: Workshop on the Future of Chiplet Architectures

Date: September 18,  2026

Time: 9:30 AM CST

Register below to receive meeting link.

Speaker 1 Lichen Weng

Title: Accelerating Chiplet Interoperability: An Open-Source Reference Design for Chiplet Systems

Abstract:

As the industry shifts toward disaggregated silicons, the Open Chiplet Atlas® (OCA) architecture provides a full-stack definition to standardize integration from physical D2D connectivity to software orchestration. This talk focuses on the OCA Harness, an open-source reference design that provides the vital non-application logic required to make chiplets system-ready.

We will perform a technical deep dive into the Harness architecture and microarchitecture, as it approaches its Beta release to the ecosystem. By decoupling application logic from interoperability infrastructures, the Harness offers a “plug-and-play” interoperability boost that slashes engineering overhead for chiplet designers and system integrators. We will share key design considerations—focusing on multi-chiplet protocol alignment and standardized system-level communications—to demonstrate how this reference design serves as the essential bridge for affordable, scalable chiplet systems.

BIO:

Lichen Weng is an SoC Architect at Tenstorrent, working on next-gen chiplet-based products and the Open Chiplet Atlas® (OCA) architecture. Prior to Tenstorrent, Lichen spent several years as an SoC Architect at Intel, where he contributed to multiple generations of data center CPUs. Lichen holds a Ph.D. in Computer Engineering, with research specializing in dynamic scheduling and resource management for multicore, multithreaded systems.

Speaker 2: Rob Pelt 

Title: Characterizing Protocol Efficiency at the Chiplet Interface

Abstract:

As chiplet integration becomes the dominant SoC packaging strategy, the efficiency with which protocol traffic fills a link’s atomic transmission unit—the flit—has become a first-order design concern. Fixed overhead, alignment constraints, and multi-protocol multiplexing all reduce usable flit capacity, and the impact of these inefficiencies depends heavily on how effectively a packing strategy can leverage knowledge of traffic structure.

This talk characterizes flit-packing efficiency across the spectrum from general-purpose to protocol-specialized approaches. At the flexible end, we examine the interactions among container sizing, flit-boundary spanning behavior, and mixed-protocol traffic. At the specialized end, we show how fixed transaction structures enable more aggressive techniques, including multi-channel interleaving, rollover management for data spanning flit boundaries, and optimized flit-packing modes.

We conclude by exploring the efficiency trade-offs between flexibility and specialization, and by offering practical guidance for protocol designers and SiP architects navigating these design choices.

BIO:

Rob Pelt is an AMD Fellow specializing in chiplet architecture. Rob serves as chair of the UALink Chiplet Workgroup and co-leads the OCP Chiplet Systems and Architecture workstream. With more than 25 years of experience, Rob has developed SoC and FPGA architectures at Intel, Ericsson, Altera, and Motorola. Rob holds both a BSEE and an MSEE from Illinois Tech.

Speaker 3: Arvind Kumar

Title: Chiplet Architectures and Advanced Packaging for Scaling AI Workloads

Abstract:

The growth of generative and agentic AI has imposed unprecedented increases in compute, memory, and bandwidth requirements, along with thermal and power delivery constraints. Chiplet architectures and advanced packaging offer a promising path to meeting these demands through much more tightly integrated compute and memory units, enabling higher compute densities and bandwidths with lower latency and power. Starting from IBM’s enterprise AI accelerator chip SpyreTM, I will discuss how chiplet architectures can enable AI system scale up and scale out. In addition, heterogeneous integration coupled with open interface standards can enable targeted architectures which can address a diverse set of workloads through co-packaging of chiplets from different sources. Finally, advanced packaging is emerging as the key enabler of next-generation AI and high-performance computing systems. I will discuss how IBM’s deep investments in AI and advanced packaging can lead to new opportunities through the emerging chiplet ecosystem.

BIO:

Dr. Arvind Kumar is a Principal Researcher and Manager at IBM Research where he leads a team focusing on next generation AI Hardware and heterogeneous integration. He has presented several invited talks and served as a panelist and short-course instructor in this area at major conferences.  He holds over 100 patents and is an IBM Master Inventor. Dr. Kumar earned SB, SM, and PhD degrees in Electrical Engineering and Computer Science, all from MIT.